ORT8850H AGERE [Agere Systems], ORT8850H Datasheet - Page 46

• Manufacturer Part Number: ORT8850H
• Description: Field-Programmable System Chip (FPSC) Eight-Channel x 850 Mbits/s Backplane Transceiver
• Manufacturer: AGERE [Agere Systems]

ORCA ORT8850 FPSC
Eight-Channel x 850 Mbits/s Backplane Transceiver
Memory Map
Table 12. Memory Map Descriptions (continued)
46
serial port output MUX
select for ch#1
serial port output MUX
select for ch#3
parallel port output MUX
select for ch#1
parallel port output MUX
select for ch#3
serial port output MUX
select for ch#5
parallel port output MUX
select for ch#7
serial port output MUX
select for ch#5
parallel port output MUX
select for ch#7
FIFO aligner threshold
value (min) Default = 2
FIFO aligner threshold
value (max) Default = 15
number of consecutive
A1 A2 errors to generate
[0:3]
A1 error insert value
[0:7]
A2 error insert value
[0:7]
backplane side loop-
back control
Bit/Register Name(S)
(continued)
Bit/ Register
Location
0C [0:3]
0D [0:7]
0A [0:4]
0B [0:4]
0E [0:7]
0C [4]
(Hex)
09 [0]
09 [1]
09 [2]
09 [3]
09 [4]
09 [5]
09 [6]
09 [7]
Register
Type
creg
creg
creg
creg
Reset
Value
(Hex)
A8
40
00
00
00
1
1
1
1
0
These are the minimum and maximum thresholds
values for the per channel receive direction align-
ment FIFOs. If and when the minimum or maximum
threshold value is violated by a particular channel,
then the interrupt event “FIFO aligner threshold
error” will be generated for that channel and latched
as a “FIFO aligner threshold error flag” in the
respective per STS-12 interrupt alarm register.
The allowable range for minimum threshold values
is 1 to 23.
The allowable range for maximum threshold values
is 0 to 22.
Note that the minimum and maximum FIFO aligner
threshold values apply to all four channels.
These three per device control signals are used in
conjunction with the per channel “a1 a2 error insert
command” control bits to force A1 A2 errors in the
transmit direction.
If a particular channel’s “a1 a2 error insert com-
mand” control bit is set to the value 1 then the “A1
and A2 error insert values” will be inserted into that
channels respective A1 and A2 bytes. The number
of consecutive frames to be corrupted is deter-
mined by the “number of consecutive A1 A2 errors
to generate[0:3]” control bits.
The error insertion is based on a rising edge detec-
tor. As such the control must be set to value 0
before trying to initiate a second a1 a2 corruption.
serial port output MUX
0
1
parallel port output
0
1
0
1
No loopback.
rx to tx loopback on backplane side. Serial input is run through
SERDES and looped back in parallel to SERDES and out
serial.
Parallel output data bus is multiplexed to
next channel.
Parallel output data bus is multiplexed to
same channel
TOH output is multiplexed to next channel.
TOH output is multiplexed to same channel.
Description
Agere Systems Inc.
August 2001
Data Sheet