ORT8850H AGERE [Agere Systems], ORT8850H Datasheet - Page 36

• Manufacturer Part Number: ORT8850H
• Description: Field-Programmable System Chip (FPSC) Eight-Channel x 850 Mbits/s Backplane Transceiver
• Manufacturer: AGERE [Agere Systems]

ORCA ORT8850 FPSC
Eight-Channel x 850 Mbits/s Backplane Transceiver
RapidIO Interface to Pi-Sched
Transmit Cell Interface
The transmit interface performs multiplexing of 32 bits of low-speed data onto four sequential octets of eight pairs
of LVDS signal pins using both edges of a high-speed clock. The transmitter module consists of the following
ten LVDS signal pairs (see Figure 15):
The high-speed data outputs (TXD[0:7]) as well as the start-of-cell signal TXSOC are generated as a result of the
positive edge of PFCLK. This is accomplished by multiplexing between the even and odd bytes of the data at a
1/2 PFCLK rate. PFCLK is derived from the internal PLL and operates at 4x the base frequency or between
240 MHz and 284 MHz. The PFCLK is expected to have a duty cycle of 47% to 53% with no more than 150 ps of
jitter. The duty cycle of PFCLK will directly affect the accuracy of the high-speed clock and its ability to maintain the
eye of the data. The 90 degree phase shift of the output clock puts TXCLK in the eye of the data.
36
(60 MHz—146 MHz)
Eight LVDS data pairs (TXD), double-edge clocked by the LVDS clock TXCLK. The data pairs carry biphase data
at 120 MHz—311 MHz.
One start-of-cell LVDS pair that indicates that octet 0 of a data cell is on TXD. The transitions of this signal are at
90 degrees also with the crossing points of the LVDS clock (TXCLK).
One LVDS clock pair output TXCLK operating at 120 MHz—311 MHz. Its relationship is intended to be exactly in
90 degree phase with the transitions of TXD data and TXSOC.
UTXD
[31:0]
WUTXCLK
UTXSOC
PLL
TRANSMIT
COMMON
FIFO
PFCLK (4x OUTPUT CLOCK FROM PLL)
(240 MHz—584 MHz)
Figure 15. RapidIO Transmit Cell Interface
ODD BYTE
EVEN BYTE
(continued)
SOC
CONTROLLER
NEGATIVE-
POSITIVE-
REGISTER
FLOPS
32 TO 8
FLOPS
EDGE
INPUT
EDGE
MUX
SOC
ODD BYTE
EVEN BYTE
PORT CLOCK
PORT DATA
ALIGNMENT
ALIGNMENT
ALIGNMENT
ALIGNMENT
PORT DATA
PORT SOC
OUTPUT
OUTPUT
OUTPUT
OUTPUT
MUXes
MUXes
MUX
MUX
Agere Systems Inc.
TXD[7:0]
TXCLK
TXSOC
August 2001
Data Sheet
0677