ORT8850H AGERE [Agere Systems], ORT8850H Datasheet - Page 64

• Manufacturer Part Number: ORT8850H
• Description: Field-Programmable System Chip (FPSC) Eight-Channel x 850 Mbits/s Backplane Transceiver
• Manufacturer: AGERE [Agere Systems]

ORCA ORT8850 FPSC
Eight-Channel x 850 Mbits/s Backplane Transceiver
Pin Information
Table 29. FPGA Common-Function Pin Description (continued)
64
Special-Purpose Pins (Can also be used as a general I/O.)
* The FPGA States of Operation section contains more information on how to control these signals during start up. The timing of DONE
P[TBTR]CLK[1:0][
RDY/BUSY/RCLK
release is controlled by one set of bit stream options, and the timing of the simultaneous release of all other configuration pins (and the acti-
vation of all user I/Os) is controlled by a second set of options.
TDI, TCK, TMS
RD/MPI_STRB
PLL_CK[0:7]
CS0, CS1
Symbol
M[3:0]
HDC
LDC
INIT
TC]
I
I/O After configuration, if the MPI is not used, this pin is a user-programmable I/O pin.*
I/O
I/O After configuration, these pins are user-programmable I/O.*
I/O Dedicated PCM clock pins. These pins are a user-programmable I/O pins if not used by
I/O Pins dedicated for the primary clock. Input pins on the middle of each side with differential
I/O After configuration, these pins are user-programmable I/O.*
I/O During the master parallel configuration mode, RCLK is a read output signal to an external
I/O After configuration, this pin is a user-programmable I/O pin.*
I/O After configuration, this pin is a user-programmable I/O pin.*
I/O INIT is a bidirectional signal before and during configuration. During configuration, a pull-up
I/O After configuration, these pins are user-programmable I/O pins.*
O During configuration in peripheral mode, RDY/RCLK indicates another byte can be written
O High during configuration is output high until configuration is complete. It is used as a con-
O Low during configuration is output low until configuration is complete. It is used as a control
I
I
I
(continued)
During powerup and initialization, M0—M3 are used to select the configuration mode with
their values latched on the rising edge of INIT. During configuration, a pull-up is enabled.
PLLs.
pairing. They may be used as general I/O pins if not needed for clocking purposes.
If boundary scan is used, these pins are test data in, test clock, and test mode select inputs.
If boundary scan is not selected, all boundary scan functions are inhibited once configura-
tion is complete. Even if boundary scan is not used, either TCK or TMS must be held at
logic 1 during configuration. Each pin has a pull-up enabled during configuration.
to the FPGA. If a read operation is done when the device is selected, the same status is
also available on D7 in asynchronous peripheral mode.
After configuration, if the MPI is not used, this pin is a user-programmable I/O pin.*
memory. This output is not normally used.
trol output, indicating that configuration is not complete.
output, indicating that configuration is not complete.
is enabled, but an external pull-up resistor is recommended. As an active-low, open-drain
output, INIT is held low during power stabilization and internal clearing of memory. As an
active-low input, INIT holds the FPGA in the wait-state before the start of configuration.
After configuration, this pin is a user-programmable I/O pin.*
CS0 and CS1 are used in the asynchronous peripheral, slave parallel, and microprocessor
configuration modes. The FPGA is selected when CS0 is low and CS1 is high. During con-
figuration, a pull-up is enabled.
RD is used in the asynchronous peripheral configuration mode. A low on RD changes D7
into a status output. As a status indication, a high indicates ready, and a low indicates busy.
WR and RD should not be used simultaneously. If they are, the write strobe overrides.
This pin is also used as the MPI data transfer strobe.
Description
Agere Systems Inc.
August 2001
Data Sheet