ORT8850H AGERE [Agere Systems], ORT8850H Datasheet - Page 73

• Manufacturer Part Number: ORT8850H
• Description: Field-Programmable System Chip (FPSC) Eight-Channel x 850 Mbits/s Backplane Transceiver
• Manufacturer: AGERE [Agere Systems]

Data Sheet
August 2001
Agere Systems Inc.
Pin Information
Table 31. Embedded Core/FPGA Interface Signal Description (continued)
STM Clock and Control
8B/10B Mode Signals
prot_switch_aa
prot_switch_ac
prot_switch_ba
prot_switch_bc
lvds_prot_aa
lvds_prot_ab
lvds_prot_ad
lvds_prot_ba
lvds_prot_bb
lvds_prot_bd
lvds_prot_ac
lvds_prot_bc
tx_k_ctrl_aa
tx_k_ctrl_ab
tx_k_ctrl_ac
tx_k_ctrl_ad
tx_k_ctrl_ba
tx_k_ctrl_bb
tx_k_ctrl_bc
tx_k_ctrl_bd
fpga_sysclk
core_ready
cdr_clk_aa
cdr_clk_ab
cdr_clk_ac
cdr_clk_ad
cdr_clk_ba
cdr_clk_bb
cdr_clk_bc
cdr_clk_bd
Pin Name
sys_fp
line_fp
(continued)
I/O
O
O
O
O
O
O
O
O
O
O
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
System frame pulse for transmitter section.
Line frame pulse for receiver section.
System clock (sys_clk). This signal is routed onto a primary clock net inside the
FPGA, with very low skew.
STM channel protection enable for channels aa and ab. Active-high.
STM channel protection enable for channels ac and ac. Active-high.
STM channel protection enable for channels ba and bb. Active-high.
STM channel protection enable for channels bc and bd. Active-high.
LVDS buffer redundancy select for rx channel aa. Active-high for redundant link.
LVDS buffer redundancy select for rx channel aa. Active-high for redundant link.
LVDS buffer redundancy select for rx channel aa. Active-high for redundant link.
LVDS buffer redundancy select for rx channel aa. Active-high for redundant link.
LVDS buffer redundancy select for rx channel aa. Active-high for redundant link.
LVDS buffer redundancy select for rx channel aa. Active-high for redundant link.
LVDS buffer redundancy select for rx channel aa. Active-high for redundant link.
LVDS buffer redundancy select for rx channel aa. Active-high for redundant link.
During powerup and FPGA configuration sequence, the core_ready is held low. At
the end of FPGA configuration, the core_ready will be held low for six clock
(sys_clk) cycles and then go active-high. Flag indicates that the embedded core is
out of its reset state.
Recovered clock for STM slice A, channel A.
Recovered clock for STM slice A, channel B.
Recovered clock for STM slice A, channel C.
Recovered clock for STM slice A, channel D.
Recovered clock for STM slice B, channel A.
Recovered clock for STM slice B, channel B.
Recovered clock for STM slice B, channel C.
Recovered clock for STM slice B, channel D.
K control bit for channel AA.
K control bit for channel AB.
K control bit for channel AC.
K control bit for channel AD.
K control bit for channel BA.
K control bit for channel BB.
K control bit for channel BC.
K control bit for channel BD.
Eight-Channel x 850 Mbits/s Backplane Transceiver
Description
ORCA ORT8850 FPSC
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