H8S2110B RENESAS [Renesas Technology Corp], H8S2110B Datasheet - Page 21

• Manufacturer Part Number: H8S2110B
• Description: Renesas 16-Bit Single-Chip Microcomputer Renesas H8S Family/H8S/2100 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

10.6 TMR_0 and TMR_1 Cascaded Connection ...................................................................... 197
10.7 TMR_Y and TMR_X Cascaded Connection .................................................................... 198
10.8 Interrupt Sources............................................................................................................... 201
10.9 Usage Notes ...................................................................................................................... 201
Section 11 Watchdog Timer (WDT)
11.1 Features ............................................................................................................................. 207
11.2 Input/Output Pins .............................................................................................................. 209
11.3 Register Descriptions ........................................................................................................ 209
11.4 Operation .......................................................................................................................... 214
11.5 Interrupt Sources............................................................................................................... 217
11.6 Usage Notes ...................................................................................................................... 218
Section 12 Serial Communication Interface (SCI)
12.1 Features ............................................................................................................................. 221
12.2 Input/Output Pins .............................................................................................................. 223
10.6.1 16-Bit Count Mode .............................................................................................. 197
10.6.2 Compare-Match Count Mode .............................................................................. 197
10.7.1 16-Bit Count Mode .............................................................................................. 198
10.7.2 Compare-Match Count Mode .............................................................................. 198
10.7.3 Input Capture Operation ...................................................................................... 199
10.9.1 Conflict between TCNT Write and Counter Clear............................................... 201
10.9.2 Conflict between TCNT Write and Count-Up ..................................................... 202
10.9.3 Conflict between TCOR Write and Compare-Match........................................... 203
10.9.4 Conflict between Compare-Matches A and B...................................................... 203
10.9.5 Switching of Internal Clocks and TCNT Operation............................................. 204
10.9.6 Mode Setting with Cascaded Connection ............................................................ 206
10.9.7 Module Stop Mode Setting .................................................................................. 206
11.3.1 Timer Counter (TCNT)........................................................................................ 209
11.3.2 Timer Control/Status Register (TCSR) ................................................................ 210
11.4.1 Watchdog Timer Mode ........................................................................................ 214
11.4.2 Interval Timer Mode ............................................................................................ 216
11.4.3 RESO Signal Output Timing ............................................................................... 217
11.6.1 Notes on Register Access..................................................................................... 218
11.6.2 Conflict between Timer Counter (TCNT) Write and Increment.......................... 219
11.6.3 Changing Values of CKS2 to CKS0 Bits............................................................. 219
11.6.4 Switching between Watchdog Timer Mode and Interval Timer Mode................ 219
11.6.5 System Reset by RESO Signal............................................................................. 220
11.6.6 Counter Values during Transitions between High-Speed, Sub-Active,
and Watch Modes ................................................................................................ 220
.............................................................................. 207
Rev. 2.00 Mar 21, 2006 page xxi of xxxviii
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