H8S2110B RENESAS [Renesas Technology Corp], H8S2110B Datasheet - Page 357

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H8S2110B

Manufacturer Part Number
H8S2110B
Description
Renesas 16-Bit Single-Chip Microcomputer Renesas H8S Family/H8S/2100 Series
Manufacturer
RENESAS [Renesas Technology Corp]
Datasheet
13.4.6
If the slave address matches to the address in the first frame (address reception frame) following
the start condition detection when the 8th bit data (R/W) is 1 (read), the TRS bit in ICCR is
automatically set to 1 and the mode changes to slave transmit mode.
Figure 13.23 shows the sample flowchart for the operations in slave transmit mode.
No
Slave Transmit Operation
Write transmit data in ICDR
No
No
Clear ACKE to 0 in ICCR
Set TRS = 0 in ICCR
Read ACKB in ICSR
Slave transmit mode
Clear IRIC in ICCR
Clear IRIC in ICCR
Clear IRIC in ICCR
Read IRIC in ICCR
Clear IRIC in ICCR
Read IRIC in ICCR
(ACKB = 0 clear)
of transmission
(ACKB = 1)?
Read ICDR
IRIC = 1?
IRIC = 1?
Figure 13.23 Sample Flowchart for Slave Transmit Mode
End
End
Yes
Yes
Yes
[3], [4] Wait for 1 byte to be transmitted.
[6] Read IRIC in ICCR
[1], [2] If the slave address matches to the address in the first frame
[7] Clear acknowledge bit data
[8] Set slave receive mode.
[9] Dummy read (to release the SCL line).
[10] Wait for stop condition
[3], [5] Set transmit data for the second and subsequent bytes.
[4] Determine end of transfer.
following the start condition detection and the R/W bit is 1
in slave recieve mode, the mode changes to slave transmit mode.
Rev. 2.00 Mar 21, 2006 page 319 of 518
Section 13 I
2
C Bus Interface (IIC)
REJ09B0299-0200

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