H8S2110B RENESAS [Renesas Technology Corp], H8S2110B Datasheet - Page 60

• Manufacturer Part Number: H8S2110B
• Description: Renesas 16-Bit Single-Chip Microcomputer Renesas H8S Family/H8S/2100 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 2 CPU
2.4.2
This 24-bit counter indicates the address of the next instruction the CPU will execute. The length
of all CPU instructions is 2 bytes (one word), so the least significant PC bit is ignored. (When an
instruction is fetched for read, the least significant PC bit is regarded as 0.)
2.4.3
EXR does not affect operation in this LSI.
Bit
7
6 to 3
2 to 0
2.4.4
This 8-bit register contains internal CPU status information, including an interrupt mask bit (I) and
half-carry (H), negative (N), zero (Z), overflow (V), and carry (C) flags. Operations can be
performed on the CCR bits by the LDC, STC, ANDC, ORC, and XORC instructions. The N, Z, V,
and C flags are used as branching conditions for conditional branch (Bcc) instructions.
Rev. 2.00 Mar 21, 2006 page 22 of 518
REJ09B0299-0200
Bit Name
T
—
I2
I1
I0
Program Counter (PC)
Extended Control Register (EXR)
Condition-Code Register (CCR)
Initial Value R/W
0
All 1
1
1
1
SP (ER7)
R/W
—
R/W
R/W
R/W
Figure 2.8 Stack
Description
Trace Bit
Does not affect operation in this LSI.
Reserved
These bits are always read as 1.
Interrupt Mask Bits 2 to 0
Do not affect operation in this LSI.
Free area
Stack area