H8S2110B RENESAS [Renesas Technology Corp], H8S2110B Datasheet - Page 360

• Manufacturer Part Number: H8S2110B
• Description: Renesas 16-Bit Single-Chip Microcomputer Renesas H8S Family/H8S/2100 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 13 I
13.4.7
The interrupt request flag (IRIC) is set at different times depending on the WAIT bit in ICMR, the
FS bit in SAR, and the FSX bit in SARX. If the ICDRE or ICDRF flag is set to 1, SCL is
automatically held low after one frame has been transferred in synchronization with the internal
clock. Figures 13.25 to 13.27 show the IRIC set timing and SCL control.
Rev. 2.00 Mar 21, 2006 page 322 of 518
REJ09B0299-0200
When WAIT = 0, and FS = 0 or FSX = 0 (I
SCL
SDA
IRIC
User processing
SCL
SDA
IRIC
User processing
IRIC Setting Timing and SCL Control
2
(a) Data transfer ends with ICDRE = 0 at transmission, or ICDRF = 0 at reception
(b) Data transfer ends with ICDRE = 1 at transmission, or ICDRF = 1 at reception
C Bus Interface (IIC)
7
7
7
7
Figure 13.25 IRIC Setting Timing and SCL Control (1)
8
8
8
8
2
C bus format, no wait)
9
A
9
A
Clear IRIC
Clear IRIC
1
1
Write to ICDR (transmit)
or read from ICDR (receive)
2
2
3
1
1
3
Clear IRIC