H8S2110B RENESAS [Renesas Technology Corp], H8S2110B Datasheet - Page 406

• Manufacturer Part Number: H8S2110B
• Description: Renesas 16-Bit Single-Chip Microcomputer Renesas H8S Family/H8S/2100 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 15 Host Interface LPC Interface (LPC)
Bit
0
15.3.2
Bits 6 to 0 in HICR2 control interrupts from the host interface (LPC) module to the slave
processor (this LSI). Bit 7 in HICR2 and HICR3 monitor host interface pin states.
The pin states can be monitored regardless of the host interface operating state or the operating
state of the functions that use pin multiplexing.
Bit
7
6
5
Rev. 2.00 Mar 21, 2006 page 368 of 518
REJ09B0299-0200
HICR2
Bit Name Initial Value Slave Host Description
LSCIB
Bit Name Initial Value Slave Host Description
GA20
LRST
SDWN
Host Interface Control Registers 2 and 3 (HICR2, HICR3)
0
Undefined
0
0
R/W
R
R/(W) * —
R/(W) * —
R/W
R/W
—
—
LSCI output Bit
Controls LSCI output in combination with the LSCIE
bit in HICR1. For details, refer to description on the
LSCIE bit.
GA20 Pin Monitor
LPC Reset Interrupt Flag
This bit is a flag that generates an ERRI interrupt
when an LPC hardware reset occurs.
0: [Clearing condition]
Writing 0 after reading LRST = 1
1: [Setting condition]
LRESET pin falling edge detection
LPC Shutdown Interrupt Flag
This bit is a flag that generates an ERRI interrupt
when an LPC hardware shutdown request is
generated.
0: [Clearing conditions]
1: [Setting condition]
LPCPD pin falling edge detection
Writing 0 after reading SDWN = 1
LPC hardware reset and LPC software reset