H8S2110B RENESAS [Renesas Technology Corp], H8S2110B Datasheet - Page 28

• Manufacturer Part Number: H8S2110B
• Description: Renesas 16-Bit Single-Chip Microcomputer Renesas H8S Family/H8S/2100 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Figure 5.6
Figure 5.7
Figure 5.8
Figure 5.9
Figure 5.10
Section 8 14-Bit PWM Timer (PWMX)
Figure 8.1
Figure 8.2
Figure 8.3
Figure 8.4
Figure 8.5
Figure 8.6
Section 9 16-Bit Free-Running Timer (FRT)
Figure 9.1
Figure 9.2
Figure 9.3
Figure 9.4
Figure 9.5
Figure 9.6
Figure 9.7
Figure 9.8
Figure 9.9
Figure 9.10
Figure 9.11
Figure 9.12
Figure 9.13
Figure 9.14
Figure 9.15
Figure 9.16
Figure 9.17
Figure 9.18
Figure 9.19
Figure 9.20
Rev. 2.00 Mar 21, 2006 page xxviii of xxxviii
Flowchart of Procedure Up to Interrupt Acceptance in Interrupt
Control Mode 1................................................................................................... 81
Interrupt Exception Handling ............................................................................. 82
Address Break Block Diagram ........................................................................... 84
Address Break Timing Example......................................................................... 86
Conflict between Interrupt Generation and Disabling ........................................ 87
PWM (D/A) Block Diagram............................................................................... 131
PWM (D/A) Operation ....................................................................................... 138
Output Waveform (OS = 0, DADR Corresponds to T
Output Waveform (OS = 1, DADR Corresponds to T
D/A Data Register Configuration when CFS = 1 ............................................... 141
Output Waveform when DADR = H'0207 (OS = 1)........................................... 142
Block Diagram of 16-Bit Free-Running Timer................................................... 148
Example of Pulse Output .................................................................................... 159
Increment Timing with Internal Clock Source ................................................... 159
Increment Timing with External Clock Source .................................................. 160
Timing of Output Compare A Output................................................................. 160
Clearing of FRC by Compare-Match A Signal................................................... 161
Input Capture Input Signal Timing (Usual Case) ............................................... 161
Input Capture Input Signal Timing (When ICRA to ICRD Are Read)............... 162
Buffered Input Capture Timing .......................................................................... 162
Buffered Input Capture Timing (BUFEA = 1).................................................... 163
Timing of Input Capture Flag (ICFA, ICFB, ICFC, or ICFD) Setting ............... 163
Timing of Output Compare Flag (OCFA or OCFB) Setting .............................. 164
Timing of Overflow Flag (OVF) Setting ............................................................ 164
OCRA Automatic Addition Timing ................................................................... 165
Timing of Input Capture Mask Signal Setting .................................................... 165
Timing of Input Capture Mask Signal Clearing.................................................. 166
FRC Write-Clear Conflict................................................................................... 167
FRC Write-Increment Conflict ........................................................................... 168
Conflict between OCR Write and Compare-Match
(When Automatic Addition Function Is Not Used) ............................................ 169
Conflict between OCRAR/OCRAF Write and Compare-Match
(When Automatic Addition Function Is Used) ................................................... 170
L
H
) ..................................... 140
) ..................................... 141