H8S2110B RENESAS [Renesas Technology Corp], H8S2110B Datasheet - Page 323

• Manufacturer Part Number: H8S2110B
• Description: Renesas 16-Bit Single-Chip Microcomputer Renesas H8S Family/H8S/2100 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Table 13.4 Flags and Transfer States (Master Mode)
Legend:
0:
1:
—: Previous state retained
0 : Cleared to 0
1 : Set to 1
MST
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
0-state retained
1-state retained
TRS
1
1
—
1
1
1
1
1
1
0
0
0
0
0
0
—
BBSY ESTP STOP IRTR
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
—
—
1
—
—
—
1
1
—
—
—
1
—
—
AASX AL
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
AAS
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
ADZ
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Rev. 2.00 Mar 21, 2006 page 285 of 518
ACKB ICDRF ICDRE State
0
0
—
1
0
0
0
0
0
—
—
—
—
—
—
—
Section 13 I
—
—
—
—
—
—
—
—
—
1
0
1
0
1
—
—
0
1
—
—
1
0
1
0
1
—
—
—
—
—
—
0
2
C Bus Interface (IIC)
REJ09B0299-0200
Idle state (flag
clearing required)
Start condition
detected
Wait state
Transmission end
(ACKE = 1 and
ACKB = 1)
Transmission end
with ICDRE = 0
ICDR write with the
above state
Transmission end
with ICDRE = 1
ICDR write with the
above state or after
start condition
detected
Automatic data
transfer from ICDRT
to ICDRS with the
above state
Reception end with
ICDRF = 0
ICDR read with the
above state
Reception end with
ICDRF = 1
ICDR read with the
above state
Automatic data
transfer from ICDRS
to ICDRR with the
above state
Arbitration lost
Stop condition
detected