H8S2110B RENESAS [Renesas Technology Corp], H8S2110B Datasheet - Page 371

• Manufacturer Part Number: H8S2110B
• Description: Renesas 16-Bit Single-Chip Microcomputer Renesas H8S Family/H8S/2100 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

9. Note on when I
Note: This restriction on usage can be canceled by setting the FNC1 and FNC0 bits to 1 in
10. Notes on WAIT function
In cases where the rise time of the 9th clock of SCL exceeds the stipulated value because of a
large bus load capacity or where a slave device in which a wait can be inserted by driving the
SCL pin low is used, the stop condition instruction should be issued after reading SCL after the
rise of the 9th clock pulse and determining that it is low.
Conditions to cause this phenomenon
When both of the following conditions are satisfied, the clock pulse of the 9th clock could
be outputted continuously in master mode using the WAIT function due to the failure of
the WAIT insertion after the 8th clock fall.
(1) Setting the WAIT bit of the ICMR register to 1 and operating WAIT, in master mode
(2) If the IRIC bit of interrupt flag is cleared from 1 to 0 between the fall of the 7th clock
Error phenomenon
Normally, WAIT State will be cancelled by clearing the IRIC flag bit from 1 to 0 after the
fall of the 8th clock in WAIT State. In this case, if the IRIC flag bit is cleared between the
7th clock fall and the 8th clock fall, the IRIC flag clear- data will be retained internally.
Therefore, the WAIT State will be cancelled right after WAIT insertion on 8th clock fall.
Restrictions
Please clear the IRIC flag before the rise of the 7th clock (the counter value of BC2
through BC0 should be 2 or greater), after the IRIC flag is set to 1 on the rise of the 9th
clock.
ICXR.
and the fall of the 8th clock.
SDA
IRIC
SCL
2
C bus interface stop condition instruction is issued
VIH
9th clock
Figure 13.31 Stop Condition Issuance Timing
SCL is detected as low
because the rise of the
waveform is delayed
[1] SCL = low determination
Secures a high period
[2] Stop condition instruction issuance
Rev. 2.00 Mar 21, 2006 page 333 of 518
Stop condition generation
Section 13 I
2
C Bus Interface (IIC)
REJ09B0299-0200