H8S2110B RENESAS [Renesas Technology Corp], H8S2110B Datasheet - Page 411

• Manufacturer Part Number: H8S2110B
• Description: Renesas 16-Bit Single-Chip Microcomputer Renesas H8S Family/H8S/2100 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

15.3.5
The ODR registers are 8-bit readable/writable registers for the slave processor (this LSI), and 8-bit
read-only registers for the host processor. The registers selected from the host according to the I/O
address are shown in the following table. For information on ODR3 selection, see section 15.3.3,
LPC Channel 3 Address Register (LADR3). In an LPC I/O read cycle, the data in the selected
register is transferred to the host. The initial values of ODR1 to ODR3 are undefined.
15.3.6
The TWR registers are sixteen 8-bit readable/writable registers to both the slave processor (this
LSI) and the host processor. In TWR0, however, two registers (TWR0MW and TWR0SW) are
allocated to the same address for both the host address and the slave address. TWR0MW is a
write-only register for the host processor, and a read-only register for the slave processor, while
TWR0SW is a write-only register for the slave processor and a read-only register for the host
processor. When the host and slave processors begin a write, after the respective TWR0 registers
have been written to, access right arbitration for simultaneous access is performed by checking the
status flags to see if those writes were valid. For the registers selected from the host according to
the I/O address, see section 15.3.3, LPC Channel 3 Address Register (LADR3).
Data transferred in an LPC I/O write cycle is written to the selected register; in an LPC I/O read
cycle, the data in the selected register is transferred to the host. The initial values of TWR0 to
TWR15 are undefined.
Bits 15 to 4
0000 0000 0110
0000 0000 0110
Bidirectional Data Registers 0 to 15 (TWR0 to TWR15)
Output Data Registers 1 to 3 (ODR1 to ODR3)
I/O Address
Bit 3
0
0
Bit 2
0
0
Bit 1
0
1
Bit 0
0
0
Transfer Cycle Host Register Selection
I/O read
I/O read
Section 15 Host Interface LPC Interface (LPC)
Rev. 2.00 Mar 21, 2006 page 373 of 518
ODR1 read
ODR2 read
REJ09B0299-0200