H8S2110B RENESAS [Renesas Technology Corp], H8S2110B Datasheet - Page 438

• Manufacturer Part Number: H8S2110B
• Description: Renesas 16-Bit Single-Chip Microcomputer Renesas H8S Family/H8S/2100 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 15 Host Interface LPC Interface (LPC)
15.4.5
A host interrupt request can be issued from the host interface by means of the SERIRQ pin. In a
host interrupt request via the SERIRQ pin, LCLK cycles are counted from the start frame of the
serialized interrupt transfer cycle generated by the host or a peripheral function, and a request
signal is generated by the frame corresponding to that interrupt. The timing is shown in figure
15.6.
The frame configuration of the serialized interrupt transfer cycle is as follows. Two of the states
comprising each frame are the recover state in which the SERIRQ signal is returned to the 1-level
at the end of the frame, and the turnaround state in which the SERIRQ signal is not driven. The
recover state must be driven by the host or slave processor that was driving the preceding state.
Rev. 2.00 Mar 21, 2006 page 400 of 518
REJ09B0299-0200
LCLK
SERIRQ
Drive source
LCLK
SERIRQ
Driver
Legend:
H: Host control
SL: Slave control
R: Recovery
Host Interface Serialized Interrupt Operation (SERIRQ)
IRQ14 frame
S
IRQ1
None
SL
or
H
T: Turnaround
S: Sample
I: Idle
R
T
START
Host controller
Start frame
H
IRQ15 frame
S
IRQ15
Figure 15.6 SERIRQ Timing
R
R
T
IOCHCK frame
T
S
None
S
IRQ0 frame
R
None
R
T
T
I
S
IRQ1 frame
IRQ1
Host controller
Stop frame
STOP
H
R
T
R
S
IRQ2 frame
T
None
R
Next cycle
T
START