MA330013 Microchip Technology, MA330013 Datasheet - Page 142

• Manufacturer Part Number: MA330013
• Description: MODULE PLUG-IN DSPIC33 100TQFP
• Manufacturer: Microchip Technology

Specifications of MA330013

• Accessory Type: Plug-In Module (PIM) - dsPIC33FJ256MC710
• Tool / Board Applications: General Purpose MCU, MPU, DSP, DSC
• Mcu Supported Families: DsPIC33
• Silicon Manufacturer: Microchip
• Core Architecture: DsPIC
• Core Sub-architecture: DsPIC33
• Silicon Core Number: DsPIC33F
• Silicon Family Name: DsPIC33FJxxMCxxx
• Rohs Compliant: Yes
• For Use With: DM330023 - BOARD DEV DSPICDEM MCHV
• Lead Free Status / RoHS Status: Not applicable / Not applicable
• For Use With/related Products: Explorer 16 (DM240001 or DM240002)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Not applicable / Not applicable

dsPIC33F
REGISTER 7-1:
DS70165E-page 140
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10-6
bit 5-4
bit 3-2
bit 1-0
R/W-0
CHEN
U-0
—
CHEN: Channel Enable bit
1 = Channel enabled
0 = Channel disabled
SIZE: Data Transfer Size bit
1 = Byte
0 = Word
DIR: Transfer Direction bit (source/destination bus select)
1 = Read from DMA RAM address, write to peripheral address
0 = Read from peripheral address, write to DMA RAM address
HALF: Early Block Transfer Complete Interrupt Select bit
1 = Initiate block transfer complete interrupt when half of the data has been moved
0 = Initiate block transfer complete interrupt when all of the data has been moved
NULLW: Null Data Peripheral Write Mode Select bit
1 = Null data write to peripheral in addition to DMA RAM write (DIR bit must also be clear)
0 = Normal operation
Unimplemented: Read as ‘0’
AMODE<1:0>: DMA Channel Operating Mode Select bits
11 = Reserved (will act as Peripheral Indirect Addressing mode)
10 = Peripheral Indirect Addressing mode
01 = Register Indirect without Post-Increment mode
00 = Register Indirect with Post-Increment mode
Unimplemented: Read as ‘0’
MODE<1:0>: DMA Channel Operating Mode Select bits
11 = One-Shot, Ping-Pong modes enabled (one block transfer from/to each DMA RAM buffer)
10 = Continuous, Ping-Pong modes enabled
01 = One-Shot, Ping-Pong modes disabled
00 = Continuous, Ping-Pong modes disabled
R/W-0
SIZE
U-0
—
DMAxCON: DMA CHANNEL x CONTROL REGISTER
W = Writable bit
‘1’ = Bit is set
R/W-0
R/W-0
DIR
AMODE<1:0>
R/W-0
R/W-0
HALF
Preliminary
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
NULLW
R/W-0
U-0
—
U-0
U-0
—
—
© 2007 Microchip Technology Inc.
x = Bit is unknown
R/W-0
U-0
—
MODE<1:0>
R/W-0
U-0
—
bit 8
bit 0