MA330013 Microchip Technology, MA330013 Datasheet - Page 219

• Manufacturer Part Number: MA330013
• Description: MODULE PLUG-IN DSPIC33 100TQFP
• Manufacturer: Microchip Technology

Specifications of MA330013

• Accessory Type: Plug-In Module (PIM) - dsPIC33FJ256MC710
• Tool / Board Applications: General Purpose MCU, MPU, DSP, DSC
• Mcu Supported Families: DsPIC33
• Silicon Manufacturer: Microchip
• Core Architecture: DsPIC
• Core Sub-architecture: DsPIC33
• Silicon Core Number: DsPIC33F
• Silicon Family Name: DsPIC33FJxxMCxxx
• Rohs Compliant: Yes
• For Use With: DM330023 - BOARD DEV DSPICDEM MCHV
• Lead Free Status / RoHS Status: Not applicable / Not applicable
• For Use With/related Products: Explorer 16 (DM240001 or DM240002)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Not applicable / Not applicable

REGISTER 18-1:
© 2007 Microchip Technology Inc.
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
bit 7
bit 6
I2CEN
R/W-0
R/W-0
GCEN
I2CEN: I2Cx Enable bit
1 = Enables the I2Cx module and configures the SDAx and SCLx pins as serial port pins
0 = Disables the I2Cx module. All I
Unimplemented: Read as ‘0’
I2CSIDL: Stop in Idle Mode bit
1 = Discontinue module operation when device enters an Idle mode
0 = Continue module operation in Idle mode
SCLREL: SCLx Release Control bit (when operating as I
1 = Release SCLx clock
0 = Hold SCLx clock low (clock stretch)
If STREN = 1:
Bit is R/W (i.e., software may write ‘0’ to initiate stretch and write ‘1’ to release clock). Hardware clear
at beginning of slave transmission. Hardware clear at end of slave reception.
If STREN = 0:
Bit is R/S (i.e., software may only write ‘1’ to release clock). Hardware clear at beginning of slave
transmission.
IPMIEN: Intelligent Peripheral Management Interface (IPMI) Enable bit
1 = IPMI mode is enabled; all addresses Acknowledged
0 = IPMI mode disabled
A10M: 10-bit Slave Address bit
1 = I2CxADD is a 10-bit slave address
0 = I2CxADD is a 7-bit slave address
DISSLW: Disable Slew Rate Control bit
1 = Slew rate control disabled
0 = Slew rate control enabled
SMEN: SMBus Input Levels bit
1 = Enable I/O pin thresholds compliant with SMBus specification
0 = Disable SMBus input thresholds
GCEN: General Call Enable bit (when operating as I
1 = Enable interrupt when a general call address is received in the I2CxRSR
0 = General call address disabled
STREN: SCLx Clock Stretch Enable bit (when operating as I
Used in conjunction with SCLREL bit.
1 = Enable software or receive clock stretching
0 = Disable software or receive clock stretching
STREN
R/W-0
(module is enabled for reception)
U-0
—
I2CxCON: I2Cx CONTROL REGISTER
U = Unimplemented bit, read as ‘0’
W = Writable bit
‘1’ = Bit is set
I2CSIDL
ACKDT
R/W-0
R/W-0
R/W-1 HC
R/W-0 HC
SCLREL
ACKEN
Preliminary
2
C pins are controlled by port functions.
HS = Set in hardware
‘0’ = Bit is cleared
R/W-0 HC
IPMIEN
R/W-0
RCEN
2
C slave)
2
C slave)
R/W-0 HC
2
R/W-0
A10M
C slave)
PEN
HC = Cleared in hardware
x = Bit is unknown
R/W-0 HC
DISSLW
dsPIC33F
R/W-0
RSEN
DS70165E-page 217
R/W-0 HC
SMEN
R/W-0
SEN
bit 8
bit 0