MA330013 Microchip Technology, MA330013 Datasheet - Page 86
![MODULE PLUG-IN DSPIC33 100TQFP](/photos/8/95/89596/ma330013_sml.jpg)
MA330013
Manufacturer Part Number
MA330013
Description
MODULE PLUG-IN DSPIC33 100TQFP
Manufacturer
Microchip Technology
Specifications of MA330013
Accessory Type
Plug-In Module (PIM) - dsPIC33FJ256MC710
Tool / Board Applications
General Purpose MCU, MPU, DSP, DSC
Mcu Supported Families
DsPIC33
Silicon Manufacturer
Microchip
Core Architecture
DsPIC
Core Sub-architecture
DsPIC33
Silicon Core Number
DsPIC33F
Silicon Family Name
DsPIC33FJxxMCxxx
Rohs Compliant
Yes
For Use With
DM330023 - BOARD DEV DSPICDEM MCHV
Lead Free Status / RoHS Status
Not applicable / Not applicable
For Use With/related Products
Explorer 16 (DM240001 or DM240002)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Not applicable / Not applicable
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dsPIC33F
REGISTER 5-1:
DS70165E-page 84
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15
bit 14
bit 13-9
bit 8
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
Note 1:
TRAPR
R/W-0
R/W-0
EXTR
2:
All of the Reset status bits may be set or cleared in software. Setting one of these bits in software does not
cause a device Reset.
If the FWDTEN Configuration bit is ‘1’ (unprogrammed), the WDT is always enabled, regardless of the
SWDTEN bit setting.
TRAPR: Trap Reset Flag bit
1 = A Trap Conflict Reset has occurred
0 = A Trap Conflict Reset has not occurred
IOPUWR: Illegal Opcode or Uninitialized W Access Reset Flag bit
1 = An illegal opcode detection, an illegal address mode or uninitialized W register used as an
0 = An illegal opcode or uninitialized W Reset has not occurred
Unimplemented: Read as ‘0’
VREGS: Voltage Regulator Standby During Sleep bit
1 = Voltage regulator goes into Standby mode during Sleep
0 = Voltage regulator is active during Sleep
EXTR: External Reset (MCLR) Pin bit
1 = A Master Clear (pin) Reset has occurred
0 = A Master Clear (pin) Reset has not occurred
SWR: Software Reset (Instruction) Flag bit
1 = A RESET instruction has been executed
0 = A RESET instruction has not been executed
SWDTEN: Software Enable/Disable of WDT bit
1 = WDT is enabled
0 = WDT is disabled
WDTO: Watchdog Timer Time-out Flag bit
1 = WDT time-out has occurred
0 = WDT time-out has not occurred
SLEEP: Wake-up from Sleep Flag bit
1 = Device has been in Sleep mode
0 = Device has not been in Sleep mode
IDLE: Wake-up from Idle Flag bit
1 = Device was in Idle mode
0 = Device was not in Idle mode
BOR: Brown-out Reset Flag bit
1 = A Brown-out Reset has occurred
0 = A Brown-out Reset has not occurred
IOPUWR
R/W-0
R/W-0
SWR
Address Pointer caused a Reset
RCON: RESET CONTROL REGISTER
W = Writable bit
‘1’ = Bit is set
SWDTEN
R/W-0
U-0
—
(2)
WDTO
R/W-0
U-0
Preliminary
—
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
SLEEP
R/W-0
(2)
U-0
—
(1)
R/W-0
IDLE
U-0
—
© 2007 Microchip Technology Inc.
x = Bit is unknown
R/W-1
BOR
U-0
—
VREGS
R/W-0
R/W-1
POR
bit 8
bit 0
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