OM11077 NXP Semiconductors, OM11077 Datasheet - Page 199

• Manufacturer Part Number: OM11077
• Description: MODULE DIMM LPC2478 ARM7
• Manufacturer: NXP Semiconductors

Specifications of OM11077

• Accessory Type: Module Card
• For Use With/related Products: ARM-57TS-LPC2478
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 568-4742

NXP Semiconductors
Table 160. GPIO interrupt register map
[1]
UM10237_4
User manual
Generic
Name
IntEnR
IntEnF
IntStatR
IntStatF
IntClr
IntStatus
Reset value reflects the data stored in used bits only. It does not include reserved bits content.
Description
GPIO Interrupt Enable for Rising edge.
GPIO Interrupt Enable for Falling edge.
GPIO Interrupt Status for Rising edge.
GPIO Interrupt Status for Falling edge.
GPIO Interrupt Clear.
GPIO overall Interrupt Status.
6.1 GPIO port Direction register IODIR and FIODIR(IO[0/1]DIR -
0xE002 80[0/1]8 and FIO[0/1/2/3/4]DIR - 0x3FFF C0[0/2/4/6/8]0)
This word accessible register is used to control the direction of the pins when they are
configured as GPIO port pins. Direction bit for any pin must be set according to the pin
functionality.
Remark: GPIO pins P0.29 and P0.30 are shared with the USB D+/− pins and must have
the same direction. If either P0DIR bits 29 or 30 are configured LOW in the IO0DIR or
FIO0DIR registers, both, P0.29 and P0.30, are inputs. If both, P0DIR bit 29 and bit 30 are
HIGH, both, P0.29 and P0.30, are outputs.
Legacy registers are the IO0DIR and IO1DIR while the enhanced GPIO functions are
supported via the FIO0DIR, FIO1DIR, FIO2DIR, FIO3DIR and FIO4DIR registers.
Table 161. GPIO port Direction register (IO0DIR - address 0xE002 8008 and IO1DIR - address
Table 162. Fast GPIO port Direction register (FIO[0/1/2/3/4]DIR - address
Bit
31:0
Bit
31:0
Symbol
P0xDIR
or
P1xDIR
Symbol
FP0xDIR
FP1xDIR
FP2xDIR
FP3xDIR
FP4xDIR
0xE002 8018) bit description
0x3FFF C0[0/2/4/6/8]0) bit description
Value Description
0
1
Value Description
0
1
Rev. 04 — 26 August 2009
Slow GPIO Direction PORTx control bits. Bit 0 in IOxDIR
controls pin Px.0, bit 31 IOxDIR controls pin Px.31.
Controlled pin is an input pin.
Controlled pin is an output pin.
Fast GPIO Direction PORTx control bits. Bit 0 in FIOxDIR
controls pin Px.0, bit 31 in FIOxDIR controls pin Px.31.
Controlled pin is input.
Controlled pin is output.
Chapter 10: LPC24XX General Purpose Input/Output (GPIO)
Access Reset
R/W
R/W
RO
RO
WO
RO
value
0x0
0x0
0x0
0x0
0x0
0x00
[1]
PORTn Register
Address & Name
IO0IntEnR - 0xE002 8090
IO2IntEnR - 0xE002 80B0
IO0IntEnR - 0xE002 8094
IO2IntEnR - 0xE002 80B4
IO0IntStatR - 0xE002 8084
IO2IntStatR - 0xE002 80A4
IO0IntStatF - 0xE002 8088
IO2IntStatF - 0xE002 80A8
IO0IntClr - 0xE002 808C
IO2IntClr - 0xE002 80AC
IOIntStatus - 0xE002 8080
UM10237
© NXP B.V. 2009. All rights reserved.
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Reset
value
0x0
Reset
value
0x0