OM11077 NXP Semiconductors, OM11077 Datasheet - Page 745
OM11077
Manufacturer Part Number
OM11077
Description
MODULE DIMM LPC2478 ARM7
Manufacturer
NXP Semiconductors
Specifications of OM11077
Accessory Type
Module Card
For Use With/related Products
ARM-57TS-LPC2478
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
568-4742
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4. Pin description
5. Register description
UM10237_4
User manual
Table 679. ETM configuration
[1]
Table 680. ETM pin description
The ETM contains 29 registers as shown in
detail in the ARM IHI 0014E document published by ARM Limited.
Resource number/type
External Inputs
External Outputs
FIFOFULL Present
FIFO depth
Trace Packet Width
Pin Name
TRACECLK
PIPESTAT[2:0]
TRACESYNC
TRACEPKT[3:0] Output Trace Packet. The trace packet signals are used to output packaged
EXTIN[0]
For details refer to ARM documentation "Embedded Trace Macrocell Specification (ARM IHI 0014E)".
Type
Output Trace Clock. The trace clock signal provides the clock for the trace
Output Pipe Line status. The pipeline status signals provide a cycle-by-cycle
Output Trace synchronization. The trace sync signal is used to indicate the
Input
Rev. 04 — 26 August 2009
Description
port. PIPESTAT[2:0], TRACESYNC, and TRACEPKT[3:0] signals are
referenced to the rising edge of the trace clock. This clock is not
generated by the ETM block. It is to be derived from the system clock.
The clock should be balanced to provide sufficient hold time for the
trace data signals. Half rate clocking mode is supported. Trace data
signals should be shifted by a clock phase from TRACECLK. Refer to
Figure 3.14 page 3.26 and figure 3.15 page 3.27 in "ETM7 Technical
Reference Manual" (ARM DDI 0158B) , for example circuits that
implements both half-rateclocking and shifting of the trace data with
respect to the clock. For TRACECLK timings refer to section 5.2 on
page 5-13 in "Embedded Trace Macrocell Specification" (ARM IHI
0014E) .
indication of what is happening in the execution stage of the processor
pipeline.
first packet of a group of trace packets and is asserted HIGH only for
the first packet of any branch address.
address and data information related to the pipeline status. All packets
are eight bits in length. A packet is output over two cycles. In the first
cycle, Packet[3:0] is output and in the second cycle, Packet[7:4] is
output.
External Trigger Input
Chapter 34: LPC24XX Embedded Trace Module (ETM)
Table 34–681
Small
2
0
Yes (Not wired)
10 bytes
4/8
[1]
below. They are described in
UM10237
© NXP B.V. 2009. All rights reserved.
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