OM11077 NXP Semiconductors, OM11077 Datasheet - Page 203
OM11077
Manufacturer Part Number
OM11077
Description
MODULE DIMM LPC2478 ARM7
Manufacturer
NXP Semiconductors
Specifications of OM11077
Accessory Type
Module Card
For Use With/related Products
ARM-57TS-LPC2478
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
568-4742
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UM10237_4
User manual
6.4 GPIO port Pin value register IOPIN and FIOPIN (IO[0/1]PIN -
Aside from the 32-bit long and word only accessible FIOCLR register, every fast GPIO
port can also be controlled via several byte and half-word accessible registers listed in
Table
additional registers allow easier and faster access to the physical port pins.
Table 169. Fast GPIO port output Clear byte and half-word accessible register description
0xE002 80[0/1]0 and FIO[0/1/2/3/4]PIN - 0x3FFF C0[1/3/5/7/9]4)
This register provides the value of port pins that are configured to perform only digital
functions. The register will give the logic value of the pin regardless of whether the pin is
configured for input or output, or as GPIO or an alternate digital function. As an example,
a particular port pin may have GPIO input, GPIO output, UART receive, and PWM output
as selectable functions. Any configuration of that pin will allow its current logic state to be
read from the corresponding IOPIN register.
If a pin has an analog function as one of its options, the pin state cannot be read if the
analog configuration is selected. Selecting the pin as an A/D input disconnects the digital
features of the pin. In that case, the pin value read in the IOPIN register is not valid.
Generic
Register
name
FIOxCLR0 Fast GPIO Port x output
FIOxCLR1 Fast GPIO Port x output
FIOxCLR2 Fast GPIO Port x output
FIOxCLR3 Fast GPIO Port x output
FIOxCLRL Fast GPIO Port x output
FIOxCLRU Fast GPIO Port x output
10–169, too. Next to providing the same functions as the FIOCLR register, these
Description
Clear register 0. Bit 0 in
FIOxCLR0 register
corresponds to pin Px.0 ... bit
7 to pin Px.7.
Clear register 1. Bit 0 in
FIOxCLR1 register
corresponds to pin Px.8 ... bit
7 to pin Px.15.
Clear register 2. Bit 0 in
FIOxCLR2 register
corresponds to pin Px.16 ...
bit 7 to pin Px.23.
Clear register 3. Bit 0 in
FIOxCLR3 register
corresponds to pin Px.24 ...
bit 7 to pin Px.31.
Clear Lower half-word
register. Bit 0 in FIOxCLRL
register corresponds to pin
Px.0 ... bit 15 to pin Px.15.
Clear Upper half-word
register. Bit 0 in FIOxCLRU
register corresponds to pin
Px.16 ... bit 15 to Px.31.
Rev. 04 — 26 August 2009
Chapter 10: LPC24XX General Purpose Input/Output (GPIO)
Register
length (bits)
& access
8 (byte)
WO
8 (byte)
WO
8 (byte)
WO
8 (byte)
WO
16 (half-word)
WO
16 (half-word)
WO
Reset
value
0x00
0x00
0x00
0x00
0x0000 FIO0CLRL - 0x3FFF C01C
0x0000 FIO0CLRU - 0x3FFF C01E
PORTn Register
Address & Name
FIO0CLR0 - 0x3FFF C01C
FIO1CLR0 - 0x3FFF C03C
FIO2CLR0 - 0x3FFF C05C
FIO3CLR0 - 0x3FFF C07C
FIO4CLR0 - 0x3FFF C09C
FIO0CLR1 - 0x3FFF C01D
FIO1CLR1 - 0x3FFF C03D
FIO2CLR1 - 0x3FFF C05D
FIO3CLR1 - 0x3FFF C07D
FIO4CLR1 - 0x3FFF C09D
FIO0CLR2 - 0x3FFF C01E
FIO1CLR2 - 0x3FFF C03E
FIO2CLR2 - 0x3FFF C05E
FIO3CLR2 - 0x3FFF C07E
FIO4CLR2 - 0x3FFF C09E
FIO0CLR3 - 0x3FFF C01F
FIO1CLR3 - 0x3FFF C03F
FIO2CLR3 - 0x3FFF C05F
FIO3CLR3 - 0x3FFF C07F
FIO4CLR3 - 0x3FFF C09F
FIO1CLRL - 0x3FFF C03C
FIO2CLRL - 0x3FFF C05C
FIO3CLRL - 0x3FFF C07C
FIO4CLRL - 0x3FFF C09C
FIO1CLRU - 0x3FFF C03E
FIO2CLRU - 0x3FFF C05E
FIO3CLRU - 0x3FFF C07E
FIO4CLRU - 0x3FFF C09E
UM10237
© NXP B.V. 2009. All rights reserved.
203 of 792
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