OM11077 NXP Semiconductors, OM11077 Datasheet - Page 722

• Manufacturer Part Number: OM11077
• Description: MODULE DIMM LPC2478 ARM7
• Manufacturer: NXP Semiconductors

Specifications of OM11077

• Accessory Type: Module Card
• For Use With/related Products: ARM-57TS-LPC2478
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 568-4742

NXP Semiconductors
UM10237_4
User manual
6.1.2 Interrupt Terminal Count Status Register (DMACIntTCStatus - 0xFFE0 4004)
6.1.3 Interrupt Terminal Count Clear Register (DMACIntClear - 0xFFE0 4008)
6.1.4 Interrupt Error Status Register (DMACIntErrorStatus - 0xFFE0 400C)
Table 653. Interrupt Status register (DMACIntStatus - address 0xFFE0 4000) bit description
The DMACIntTCStatus Register is read-only and indicates the status of the terminal count
after masking.
Register.
Table 654. Interrupt Terminal Count Status register (DMACIntTCStatus - address
The DMACIntTCClear Register is write-only and clears a terminal count interrupt request.
When writing to this register, each data bit that is set HIGH causes the corresponding bit
in the status register to be cleared. Data bits that are LOW have no effect on the
corresponding bit in the register.
DMACIntTCClear Register.
Table 655. Interrupt Terminal Count Clear register (DMACIntClear - address 0xFFE0 4008) bit
The DMACIntErrorStatus Register is read-only and indicates the status of the error
request after masking.
DMACIntErrorStatus Register.
Bit
0
1
31:2
Bit
0
1
31:2
Bit
0
1
31:2
Symbol
IntStatus0
IntStatus1
-
Symbol
IntTCStatus0
IntTCStatus1
-
Symbol
IntTCClear0
IntTCClear1
-
0xFFE0 4004) bit description
description
Table 32–654
Chapter 32: LPC24XX General Purpose DMA (GPDMA) controller
Rev. 04 — 26 August 2009
Table 32–656
Description
Status of channel 0 interrupts after masking.
Status of channel 1 interrupts after masking.
Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.
Description
Terminal count interrupt request status for channel 0.
Terminal count interrupt request status for channel 1.
Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.
Description
Writing a 1 clears the terminal count interrupt request for
channel 0 (IntTCStatus0).
Writing a 1 clears the terminal count interrupt request for
channel 1 (IntTCStatus1).
Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.
shows the bit assignments of the DMACIntTCStatus
Table 32–655
shows the bit assignments of the
shows the bit assignments of the
UM10237
© NXP B.V. 2009. All rights reserved.
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0
0
Reset
Value
NA
Reset
Value
0
0
NA
Reset
Value
-
-
NA