OM11077 NXP Semiconductors, OM11077 Datasheet - Page 30
OM11077
Manufacturer Part Number
OM11077
Description
MODULE DIMM LPC2478 ARM7
Manufacturer
NXP Semiconductors
Specifications of OM11077
Accessory Type
Module Card
For Use With/related Products
ARM-57TS-LPC2478
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
568-4742
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UM10237_4
User manual
3.1.3 External Interrupt Mode register (EXTMODE - 0xE01F C148)
3.1.4 External Interrupt Polarity register (EXTPOLAR - 0xE01F C14C)
The bits in this register select whether each EINT pin is level- or edge-sensitive. Only pins
that are selected for the EINT function (see
VICIntEnable register
0xFFFF
course pins selected for other functions may cause interrupts from those functions).
Note: Software should only change a bit in this register when its interrupt is
disabled in VICIntEnable, and should write the corresponding 1 to EXTINT before
enabling (initializing) or re-enabling the interrupt. An extraneous interrupt(s) could
be set by changing the mode and not having the EXTINT cleared.
Table 26.
In level-sensitive mode, the bits in this register select whether the corresponding pin is
high- or low-active. In edge-sensitive mode, they select whether the pin is rising- or
falling-edge sensitive. Only pins that are selected for the EINT function (see
Section
Register (VICIntEnable - 0xFFFF
function (though of course pins selected for other functions may cause interrupts from
those functions).
Note: Software should only change a bit in this register when its interrupt is
disabled in VICIntEnable, and should write the corresponding 1 to EXTINT before
enabling (initializing) or re-enabling the interrupt. An extraneous interrupt(s) could
be set by changing the polarity and not having the EXTINT cleared.
Bit
0
1
2
3
7:4
Symbol
EXTMODE0 0
EXTMODE1 0
EXTMODE2 0
EXTMODE3 0
-
9–5.5) and enabled in the VICIntEnable register
F010)”) can cause interrupts from the External Interrupt function (though of
External Interrupt Mode register (EXTMODE - address 0xE01F C148) bit
description
Value
1
1
1
1
-
(Section 7–3.4 “Interrupt Enable Register (VICIntEnable -
Rev. 04 — 26 August 2009
Description
Level-sensitivity is selected for EINT0.
EINT0 is edge sensitive.
Level-sensitivity is selected for EINT1.
EINT1 is edge sensitive.
Level-sensitivity is selected for EINT2.
EINT2 is edge sensitive.
Level-sensitivity is selected for EINT3.
EINT3 is edge sensitive.
Reserved, user software should not write ones to reserved
bits. The value read from a reserved bit is not defined.
F010)”) can cause interrupts from the External Interrupt
Section
Chapter 3: LPC24XX System control
9–5.5) and enabled in the
(Section 7–3.4 “Interrupt Enable
UM10237
© NXP B.V. 2009. All rights reserved.
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Reset
value
0
0
0
0
NA
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