OM11077 NXP Semiconductors, OM11077 Datasheet - Page 513

• Manufacturer Part Number: OM11077
• Description: MODULE DIMM LPC2478 ARM7
• Manufacturer: NXP Semiconductors

Specifications of OM11077

• Accessory Type: Module Card
• For Use With/related Products: ARM-57TS-LPC2478
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 568-4742

NXP Semiconductors
UM10237_4
User manual
17.2.3 Setting the interrupt pending bits (IntPnd 63 to 0)
17.2.4 Clearing the interrupt pending bits (IntPnd 63 to 0)
17.2.5 Setting the message lost bit of a FullCAN message object (MsgLost 63 to 0)
17.2.6 Clearing the message lost bit of a FullCAN message object (MsgLost 63 to
17.3.1 Scenario 1: Normal case, no message lost
17.3 Set and clear mechanism of the FullCAN interrupt
The interrupt pending bit (IntPndx) gets asserted in case of an accepted FullCAN
message and if the interrupt of the according FullCAN Object is enabled (enable bit
FCANIntxEn) is set).
During the last write access from the data storage of a FullCAN message object the
interrupt pending bit of a FullCAN object (IntPndx) gets asserted.
Each of the FullCAN Interrupt Pending requests gets cleared when the semaphore bits of
a message object are cleared by Software (ARM CPU).
The Message Lost bit of a FullCAN message object gets asserted in case of an accepted
FullCAN message and when the FullCAN Interrupt of the same object is asserted already.
During the first write access from the data storage of a FullCAN message object the
Message Lost bit of a FullCAN object (MsgLostx) gets asserted if the interrupt pending bit
is set already.
0)
The Message Lost bit of a FullCAN message object gets cleared when the FullCAN
Interrupt of the same object is not asserted.
During the first write access from the data storage of a FullCAN message object the
Message Lost bit of a FullCAN object (MsgLostx) gets cleared if the interrupt pending bit
is not set.
Special precaution is needed for the built-in set and clear mechanism of the FullCAN
Interrupts. The following text illustrates how the already existing Semaphore Bits (see
Section 18–17.1 “FullCAN message layout”
features (IntPndx, MsgLstx) will behave.
Figure 18–85
message is stored in the FullCAN Message Object Section. After storage the message is
read out by Software (ARM CPU).
below shows a typical “normal” scenario in which an accepted FullCAN
Rev. 04 — 26 August 2009
Chapter 18: LPC24XX CAN controllers CAN1/2
for more details) and how the new introduced
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