OM11077 NXP Semiconductors, OM11077 Datasheet - Page 572

• Manufacturer Part Number: OM11077
• Description: MODULE DIMM LPC2478 ARM7
• Manufacturer: NXP Semiconductors

Specifications of OM11077

• Accessory Type: Module Card
• For Use With/related Products: ARM-57TS-LPC2478
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 568-4742

1. Basic configuration
2. Features
3. Applications
4. Description
UM10237_4
User manual
The I
Interfaces to external I
etc.
A typical I
direction bit (R/W), two types of data transfers are possible on the I
1. Power: In the PCONP register
2. Clock: In PCLK_SEL0 select PCLK_I2C0; in PCLK_SEL1 select PCLK_I2C1/2 (see
3. Pins: Select I
4. Interrupts are enabled in the VIC using the VICIntEnable register
5. Initialization: see
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UM10237
Chapter 22: LPC24XX I
Rev. 04 — 26 August 2009
Remark: On reset, all I
Section
PINMODE4 (see
Remark: I
(see
Standard I
Master/Slave.
Arbitration between simultaneously transmitting masters without corruption of serial
data on the bus.
Programmable clock to allow adjustment of I
Bidirectional data transfer between masters and slaves.
Serial clock synchronization allows devices with different bit rates to communicate via
one serial bus.
Serial clock synchronization can be used as a handshake mechanism to suspend and
resume serial transfer.
The I
Data transfer from a master transmitter to a slave receiver. The first byte transmitted
by the master is the slave address. Next follows a number of data bytes. The slave
returns an acknowledge bit after each received byte.
2
C0/1/2 interfaces are configured using the following registers:
Section
2
2
C bus may be used for test and diagnostic purposes.
C bus configuration is shown in
4–3.3.4.
2
2
C0 pins SDA0 and SCL0 are open-drain outputs for I
C compliant bus interfaces that may be configured as Master, Slave, or
2
9–5.14).
C pins and their modes in PINSEL0 to PINSEL4 and PINMODE0 to
Section 22–10.1
Section
Rev. 04 — 26 August 2009
2
C standard parts, such as serial RAMs, LCDs, tone generators,
2
C interfaces are enabled (PCI2C0/1/2 = 1).
9–5).
2
(Table
C interfaces I
and
4–63), set bit PCI2C0/1/2.
Figure
Section
2
C transfer rates.
22–111. Depending on the state of the
22–9.12.1.
2
C0/1/2
2
C bus:
2
C-bus compliance
(Table
© NXP B.V. 2009. All rights reserved.
User manual
7–106).
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