OM11077 NXP Semiconductors, OM11077 Datasheet - Page 77

• Manufacturer Part Number: OM11077
• Description: MODULE DIMM LPC2478 ARM7
• Manufacturer: NXP Semiconductors

Specifications of OM11077

• Accessory Type: Module Card
• For Use With/related Products: ARM-57TS-LPC2478
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 568-4742

NXP Semiconductors
Table 67.
[1]
UM10237_4
User manual
Address
0xFFE0 8268
0xFFE0 826C EMCStatic WaitRd3
0xFFE0 8270
0xFFE0 8274
0xFFE0 8278
Reset Value reflects the data stored in used bits only. It does not include reserved bits content.
Summary of EMC registers
Register Name
EMCStatic WaitOen3
EMCStatic WaitPage3
EMCStatic WaitWr3
EMCStatic WaitTurn3
10.1 EMC Control register (EMCControl - 0xFFE0 8000)
The EMCControl register is a read/write register that controls operation of the memory
controller. The control bits can be altered during normal operation.
bit assignments for the EMCControl register.
Table 68.
Bit
0
1
Symbol
EMC Enable (E)
Address mirror (M)
EMC Control register (EMCControl - address 0xFFE0 8000) bit description
…continued
Description
Selects the delay from chip select 3 or address change,
whichever is later, to output enable.
Selects the delay from chip select 3 to a read access.
Selects the delay for asynchronous page mode
sequential accesses for chip select 3.
Selects the delay from chip select 3 to a write access.
Selects the number of bus turnaround cycles for chip
select 3.
Rev. 04 — 26 August 2009
Value Description
0
1
0
1
Chapter 5: LPC24XX External Memory Controller (EMC)
Indicates if the EMC is enabled or disabled:
Disabled
Enabled (POR and warm reset value).
Disabling the EMC reduces power consumption.
When the memory controller is disabled the memory
is not refreshed. The memory controller is enabled by
setting the enable bit, or by reset.
This bit must only be modified when the EMC is in idle
state.
Indicates normal or reset memory map:
Normal memory map.
Reset memory map. Static memory CS1 is mirrored
onto CS0 and DYCS0 (POR reset value).
On POR, CS1 is mirrored to both CS0 and DYCS0
memory areas. Clearing the M bit enables CS0 and
DYCS0 memory to be accessed.
[1]
Table 5–68
Warm
Reset
Value
[1]
-
-
-
-
-
UM10237
© NXP B.V. 2009. All rights reserved.
POR
Reset
Value
[1]
0x0
0x1F
0x1F
0x1F
0xF
shows the
77 of 792
Reset
Value
1
1
Type
R/W
R/W
R/W
R/W
R/W