OM11077 NXP Semiconductors, OM11077 Datasheet - Page 452

• Manufacturer Part Number: OM11077
• Description: MODULE DIMM LPC2478 ARM7
• Manufacturer: NXP Semiconductors

Specifications of OM11077

• Accessory Type: Module Card
• For Use With/related Products: ARM-57TS-LPC2478
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 568-4742

NXP Semiconductors
UM10237_4
User manual
4.6 UART1 FIFO Control Register (U1FCR - 0xE001 0008, Write Only)
4.7 UART1 Line Control Register (U1LCR - 0xE001 000C)
It is the lowest priority interrupt and is activated whenever there is any state change on
modem inputs pins, DCD, DSR or CTS. In addition, a low to high transition on modem
input RI will generate a modem interrupt. The source of the modem interrupt can be
determined by examining U1MSR[3:0]. A U1MSR read will clear the modem interrupt.
The U1FCR controls the operation of the UART1 RX and TX FIFOs.
Table 404. UART1 FIFO Control Register (U1FCR - address 0xE001 0008, Write Only) bit
The U1LCR determines the format of the data character that is to be transmitted or
received.
Table 405. UART1 Line Control Register (U1LCR - address 0xE001 000C) bit description
Bit
0
1
2
5:3
7:6
Bit
1:0
2
3
Symbol Value Description
Word
Length
Select
Stop Bit
Select
Parity
Enable
Symbol
FIFO
Enable
RX FIFO
Reset
TX FIFO
Reset
-
RX
Trigger
Level
description
00
01
10
11
0
1
0
1
Value Description
0
1
0
1
0
1
00
01
10
11
5 bit character length.
6 bit character length.
7 bit character length.
8 bit character length.
1 stop bit.
2 stop bits (1.5 if U1LCR[1:0]=00).
Disable parity generation and checking.
Enable parity generation and checking.
Rev. 04 — 26 August 2009
UART1 FIFOs are disabled. Must not be used in the application.
Active high enable for both UART1 Rx and TX FIFOs and
U1FCR[7:1] access. This bit must be set for proper UART1
operation. Any transition on this bit will automatically clear the
UART1 FIFOs.
No impact on either of UART1 FIFOs.
Writing a logic 1 to U1FCR[1] will clear all bytes in UART1 Rx
FIFO and reset the pointer logic. This bit is self-clearing.
No impact on either of UART1 FIFOs.
Writing a logic 1 to U1FCR[2] will clear all bytes in UART1 TX
FIFO and reset the pointer logic. This bit is self-clearing.
Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.
These two bits determine how many receiver UART1 FIFO
characters must be written before an interrupt is activated.
Trigger level 0 (1 character or 0x01).
Trigger level 1 (4 characters or 0x04).
Trigger level 2 (8 characters or 0x08).
Trigger level 3 (14 characters or 0x0E).
Chapter 17: LPC24XX UART1
UM10237
© NXP B.V. 2009. All rights reserved.
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Reset
Value
0
0
0
NA
0
Reset
Value
0
0
0