OM11077 NXP Semiconductors, OM11077 Datasheet - Page 574

• Manufacturer Part Number: OM11077
• Description: MODULE DIMM LPC2478 ARM7
• Manufacturer: NXP Semiconductors

Specifications of OM11077

• Accessory Type: Module Card
• For Use With/related Products: ARM-57TS-LPC2478
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 568-4742

NXP Semiconductors
5. Pin description
6. I
UM10237_4
User manual
2
C operating modes
6.1 Master Transmitter mode
Table 509. I
In a given application, the I
mode, the I
one of these addresses is detected, an interrupt is requested. If the processor wishes to
become the bus master, the hardware waits until the bus is free before the master mode is
entered so that a possible slave operation is not interrupted. If bus arbitration is lost in the
master mode, the I
own slave address in the same serial transfer.
In this mode data is transmitted from master to slave. Before the master transmitter mode
can be entered, the I2CONSET register must be initialized as shown in
I2EN must be set to 1 to enable the I
acknowledge any address when another device is master of the bus, so it can not enter
slave mode. The STA, STO and SI bits must be 0. The SI Bit is cleared by writing 1 to the
SIC bit in the I2CONCLR register.
Table 510. I2CnCONSET used to configure Master mode
The first byte transmitted contains the slave address of the receiving device (7 bits) and
the data direction bit. In this mode the data direction bit (R/W) should be 0 which means
Write. The first byte transmitted contains the slave address and Write bit. Data is
transmitted 8 bits at a time. After each byte is transmitted, an acknowledge bit is received.
START and STOP conditions are output to indicate the beginning and the end of a serial
transfer.
The I
I
condition is transmitted, the SI bit is set, and the status code in the I2STAT register is
0x08. This status code is used to vector to a state service routine which will load the slave
address and Write bit to the I2DAT register, and then clear the SI bit. SI is cleared by
writing a 1 to the SIC bit in the I2CONCLR register. The STA bit should be cleared after
writing the slave address.
When the slave address and R/W bit have been transmitted and an acknowledgment bit
has been received, the SI bit is set again, and the possible status codes now are 0x18,
0x20, or 0x38 for the master mode, or 0x68, 0x78, or 0xB0 if the slave mode was enabled
(by setting AA to 1). The appropriate actions to be taken for each of these status codes
are shown in
Pin
SDA0,1, 2
SCL0,1, 2
2
Bit
Symbol
Value
C logic will send the START condition as soon as the bus is free. After the START
2
C interface will enter master transmitter mode when software sets the STA bit. The
7
-
-
2
2
C Pin Description
C hardware looks for its own slave address and the general call address. If
Table 22–525
Type
Input/Output
Input/Output
2
C block switches to the slave mode immediately and can detect its
6
I2EN
1
Rev. 04 — 26 August 2009
2
C block may operate as a master, a slave, or both. In the slave
to
Table
5
STA
0
Description
I
I
2
2
C Serial Data
C Serial Clock
2
22–528.
C function. If the AA bit is 0, the I
4
STO
0
Chapter 22: LPC24XX I
3
SI
0
2
AA
0
2
C interfaces I
2
UM10237
1
-
-
C interface will not
© NXP B.V. 2009. All rights reserved.
Table
22–510.
0
-
-
574 of 792
2
C0/1/2