OM11077 NXP Semiconductors, OM11077 Datasheet - Page 653

• Manufacturer Part Number: OM11077
• Description: MODULE DIMM LPC2478 ARM7
• Manufacturer: NXP Semiconductors

Specifications of OM11077

• Accessory Type: Module Card
• For Use With/related Products: ARM-57TS-LPC2478
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 568-4742

NXP Semiconductors
Table 571. Counter Increment Select Mask register (CISS - address 0xE002 4040) bit description
UM10237_4
User manual
Bit Symbol
7
SubSecEna
6.2.6 Alarm Mask Register (AMR - 0xE002 4010)
6.3.1 Consolidated Time Register 0 (CTIME0 - 0xE002 4014)
6.3 Consolidated time registers
Value Description
0
1
The Alarm Mask Register (AMR) allows the user to mask any of the alarm registers.
Table 26–572
alarm function, every non-masked alarm register must match the corresponding time
counter for an interrupt to be generated. The interrupt is generated only when the counter
comparison first changes from no match to match. The interrupt is removed when a one is
written to the appropriate bit of the Interrupt Location Register (ILR). If all mask bits are
set, then the alarm is disabled.
Table 572. Alarm Mask Register (AMR - address 0xE002 4010) bit description
The values of the Time Counters can optionally be read in a consolidated format which
allows the programmer to read all time counters with only three read operations. The
various registers are packed into 32 bit values as shown in
and
24.
The Consolidated Time Registers are read only. To write new values to the Time
Counters, the Time Counter addresses should be used.
The Consolidated Time Register 0 contains the low order time values: Seconds, Minutes,
Hours, and Day of Week.
Bit
0
1
2
3
4
5
6
7
Subsecond interrupt enable.
The sub-second interrupt is disabled.
The sub-second interrupt is enabled.
Table
Symbol
AMRSEC
AMRMIN
AMRHOUR When 1, the Hour value is not compared for the alarm.
AMRDOM
AMRDOW
AMRDOY
AMRMON
AMRYEAR When 1, the Year value is not compared for the alarm.
26–575. The least significant bit of each register is read back at bit 0, 8, 16, or
shows the relationship between the bits in the AMR and the alarms. For the
Description
When 1, the Second value is not compared for the alarm.
When 1, the Minutes value is not compared for the alarm.
When 1, the Day of Month value is not compared for the alarm.
When 1, the Day of Week value is not compared for the alarm.
When 1, the Day of Year value is not compared for the alarm.
When 1, the Month value is not compared for the alarm.
Rev. 04 — 26 August 2009
Chapter 26: LPC24XX Real-Time Clock (RTC) and battery RAM
Table
26–573,
UM10237
© NXP B.V. 2009. All rights reserved.
Table
26–574,
653 of 792
Reset
value
NC
Reset
value
NA
NA
NA
NA
NA
NA
NA
NA