OM11077 NXP Semiconductors, OM11077 Datasheet - Page 564

• Manufacturer Part Number: OM11077
• Description: MODULE DIMM LPC2478 ARM7
• Manufacturer: NXP Semiconductors

Specifications of OM11077

• Accessory Type: Module Card
• For Use With/related Products: ARM-57TS-LPC2478
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 568-4742

NXP Semiconductors
UM10237_4
User manual
6.1 Power Control Register (MCI Power - 0xE008 C000)
6.2 Clock Control Register (MCIClock - 0xE008 C004)
Table 490. Summary of MCI registers
[1]
The MCIPower register controls an external power supply. Power can be switched on and
off, and adjust the output voltage.
MCIPower register.
The active level of the MCIPWR (Power Supply Enable) pin can be selected by bit 3 of the
SCS register (see
C1A0)” on page 36
Table 491: Power Control register (MCIPower - address 0xE008 C000) bit description
When the external power supply is switched on, the software first enters the power-up
phase, and waits until the supply output is stable before moving to the power-on phase.
During the power-up phase, MCIPWR is set HIGH. The card bus outlets are disabled
during both phases.
Note: After a data write, data cannot be written to this register for three MCLK clock
periods plus two PCLK clock periods.
The MCIClock register controls the MCICLK output.
assignment of the clock control register.
Name
MCIMask0
MCIFifoCnt
MCIFIFO
Bit
1:0
5:2
6
7
31:8
Reset Value reflects the data stored in used bits only. It does not include reserved bits content.
Symbol
Ctrl
-
OpenDrain
Rod
-
Description
Interrupt 0 mask register.
FIFO Counter.
Data FIFO Register.
Section 3–7.1 “System Controls and Status register (SCS - 0xE01F
Value Description
00
01
10
11
for details).
Rev. 04 — 26 August 2009
Power-off
Reserved
Power-up
Power-on
Reserved, user software should not write ones to
reserved bits. The value read from a reserved bit is not
defined.
MCICMD output control.
Rod control.
Reserved, user software should not write ones to
reserved bits. The value read from a reserved bit is not
defined.
Table 21–491
Chapter 21: LPC24XX SD/MMC card interface
Access Width Reset
R/W
RO
R/W
shows the bit assignment of the
Table 21–492
22
15
32
Value
0x000000
0x00000000 0xE008 C080
0x0000
shows the bit
[1]
UM10237
© NXP B.V. 2009. All rights reserved.
Address
0xE008 C03C
0xE008 C048
to
0xE008 C0BC
Reset
Value
00
NA
0
0
NA
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