OM11077 NXP Semiconductors, OM11077 Datasheet - Page 728

• Manufacturer Part Number: OM11077
• Description: MODULE DIMM LPC2478 ARM7
• Manufacturer: NXP Semiconductors

Specifications of OM11077

• Accessory Type: Module Card
• For Use With/related Products: ARM-57TS-LPC2478
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 568-4742

NXP Semiconductors
UM10237_4
User manual
6.2.3 Channel Linked List Item Registers (DMACC0LLI - 0xFFE0 4108 and
6.2.4 Channel Control Registers (DMACC0Control - 0xFFE0 410C and
Table 668. Channel Destination Address registers (DMACC0DestAddr - address
DMACC1LLI - 0xFFE0 4128)
The two read/write DMACCxLLI Registers contain a word-aligned address of the next
Linked List Item (LLI). If the LLI is 0, then the current LLI is the last in the chain, and the
DMA channel is disabled when all DMA transfers associated with it are completed.
Note: Programming this register when the DMA channel is enabled has unpredictable
side effects.
Table 32–669
Table 669. Channel Linked List Item registers (DMACC0LLI - address 0xFFE0 4108 and
Note: To make loading the LLIs more efficient for some systems, the LLI data structures
can be made four-word aligned.
DMACC0Control - 0xFFE0 412C)
The two read/write DMACCxControl Registers contain DMA channel control information
such as the transfer size, burst size, and transfer width. Each register is programmed
directly by software before the DMA channel is enabled. When the channel is enabled the
register is updated by following the linked list when a complete packet of data has been
transferred. Reading the register while the channel is active does not give useful
information. This is because by the time software has processed the value read, the
channel might have progressed. It is intended to be read only when a channel has
stopped.
Bit
31:0
Bit
0
1
31:2
Symbol
DestAddr
Symbol
Reserved Reserved, read as zero, do not modify.
R
LLI
Table 32–670
0xFFE0 4104 and DMACC1DestAddr - address 0xFFE0 4124) bit description
DMACC1LLI - address 0xFFE0 4128) bit description
shows the bit assignments of the DMACCxLLI Register.
Description
Reserved, and must be written as 0, masked on read.
Linked list item. Bits [31:2] of the address for the next LLI.
Address bits [1:0] are 0.
Description
DMA destination address
Chapter 32: LPC24XX General Purpose DMA (GPDMA) controller
Rev. 04 — 26 August 2009
shows the bit assignments of the DMACCxControl Register.
UM10237
© NXP B.V. 2009. All rights reserved.
NA
0
Reset Value
0
Reset Value
0x0000 0000
728 of 792