OM11077 NXP Semiconductors, OM11077 Datasheet - Page 241

• Manufacturer Part Number: OM11077
• Description: MODULE DIMM LPC2478 ARM7
• Manufacturer: NXP Semiconductors

Specifications of OM11077

• Accessory Type: Module Card
• For Use With/related Products: ARM-57TS-LPC2478
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 568-4742

NXP Semiconductors
8. Descriptor and status formats
UM10237_4
User manual
7.4.5 Power-Down Register (PowerDown - 0xFFE0 0FF4)
8.1 Receive descriptors and statuses
Table 231. Interrupt Set register (IntSet - address 0xFFE0 0FEC) bit description
The interrupt set register is write-only. Writing a 1 to a bit of the IntSet register sets the
corresponding bit in the status register. Writing a 0 will not affect the interrupt status.
The Power-Down register (PowerDown) is used to block all AHB accesses except
accesses to the PowerDown register. The register has an address of 0xFFE0 0FF4. The
bit definition of the register is listed in
Table 232. Power-Down register (PowerDown - address 0xFFE0 0FF4) bit description
Setting the bit will return an error on all read and write accesses on the MACAHB interface
except for accesses to the PowerDown register.
This section defines the descriptor format for the transmit and receive scatter/gather DMA
engines. Each Ethernet frame can consist of one or more fragments. Each fragment
corresponds to a single descriptor. The DMA managers in the Ethernet block scatter (for
receive) and gather (for transmit) multiple fragments for a single Ethernet frame.
Figure 11–28
Bit
0
1
2
3
4
5
6
7
11:8
12
13
31:14
Bit
30:0
31
Symbol
RxOverrunIntSet
RxErrorIntSet
RxFinishedIntSet
RxDoneIntSet
TxUnderrunIntSet
TxErrorIntSet
TxFinishedIntSet
TxDoneIntSet
-
SoftIntSet
WakeupIntSet
-
Symbol
-
PowerDownMACAHB
depicts the layout of the receive descriptors in memory.
Rev. 04 — 26 August 2009
Function
Writing a ’1’ to one of these bits (0 to 7) sets the
corresponding status bit in interrupt status register
IntStatus.
Unused
Writing a ’1’ to one of these bits (12 and/or 13) sets the
corresponding status bit in interrupt status register
IntStatus.
Unused
Function
Unused
If true, all AHB accesses will return a read/write error,
except accesses to the PowerDown register.
Table
11–232.
Chapter 11: LPC24XX Ethernet
UM10237
© NXP B.V. 2009. All rights reserved.
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Reset
value
0x0
0
0
Reset
value
0
0
0
0
0
0
0
0x0
0
0
0x0