OM11077 NXP Semiconductors, OM11077 Datasheet - Page 80

• Manufacturer Part Number: OM11077
• Description: MODULE DIMM LPC2478 ARM7
• Manufacturer: NXP Semiconductors

Specifications of OM11077

• Accessory Type: Module Card
• For Use With/related Products: ARM-57TS-LPC2478
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 568-4742

NXP Semiconductors
UM10237_4
User manual
Table 71.
[1]
[2]
[3]
Remark: Deep-sleep mode can be entered by setting the deep-sleep mode (DP) bit, the
dynamic memory clock enable bit (CE), and the dynamic clock control bit (CS) to one. The
device is then put into a low-power mode where the device is powered down and no
longer refreshed. All data in the memory is lost.
Bit
2
4:3
5
6
8:7
12:9
13
31:14 -
Clock enable must be HIGH during SDRAM initialization.
The memory controller exits from power-on reset with the self-refresh bit HIGH. To enter normal functional
mode set this bit LOW.
Disabling CLKOUT can be performed if there are no SDRAM memory transactions. When enabled this bit
can be used in conjunction with the dynamic memory clock control (CS) field.
Symbol
Self-refresh
request,
EMCSREFREQ
(SR)
-
Memory clock
control (MMC)
-
SDRAM
initialization (I)
-
Low-power
SDRAM
deep-sleep
mode (DP)
Dynamic Control register (EMCDynamicControl - address 0xFFE0 8020) bit
description
Rev. 04 — 26 August 2009
Value Description
0
1
-
0
1
-
00
01
10
11
-
0
1
-
Chapter 5: LPC24XX External Memory Controller (EMC)
Normal mode.
Enter self-refresh mode (POR reset value).
By writing 1 to this bit self-refresh can be entered under
software control. Writing 0 to this bit returns the EMC to
normal mode.
The self-refresh acknowledge bit in the EMCStatus
register must be polled to discover the current operating
mode of the EMC.
Reserved, user software should not write ones to
reserved bits. The value read from a reserved bit is not
defined.
CLKOUT enabled (POR reset value).
CLKOUT disabled.
Reserved, user software should not write ones to
reserved bits. The value read from a reserved bit is not
defined.
Issue SDRAM NORMAL operation command (POR
reset value).
Issue SDRAM MODE command.
Issue SDRAM PALL (precharge all) command.
Issue SDRAM NOP (no operation) command)
Reserved, user software should not write ones to
reserved bits. The value read from a reserved bit is not
defined.
Normal operation (POR reset value).
Enter Deep-sleep mode.
Reserved, user software should not write ones to
reserved bits. The value read from a reserved bit is not
defined.
[2]
[3]
UM10237
© NXP B.V. 2009. All rights reserved.
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Reset
Value
1
NA
0
NA
00
NA
0
NA