OM11077 NXP Semiconductors, OM11077 Datasheet - Page 627

• Manufacturer Part Number: OM11077
• Description: MODULE DIMM LPC2478 ARM7
• Manufacturer: NXP Semiconductors

Specifications of OM11077

• Accessory Type: Module Card
• For Use With/related Products: ARM-57TS-LPC2478
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 568-4742

NXP Semiconductors
UM10237_4
User manual
6.8 Match Control Register (T[0/1/2/3]MCR - 0xE000 4014, 0xE000 8014,
0xE007 0014, 0xE007 4014)
The Match Control Register is used to control what operations are performed when one of
the Match Registers matches the Timer Counter. The function of each of the bits is shown
in
Table 550: Match Control Register (T[0/1/2/3]MCR - addresses 0xE000 4014, 0xE000 8014,
Bit
0
1
2
3
4
5
6
7
8
9
10
11
15:12 -
Table
Symbol Value Description
MR0I
MR0R
MR0S
MR1I
MR1R
MR1S
MR2I
MR2R
MR2S
MR3I
MR3R
MR3S
24–550.
0xE007 0014, 0xE007 4014) bit description
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
Rev. 04 — 26 August 2009
Interrupt on MR0: an interrupt is generated when MR0 matches
the value in the TC.
This interrupt is disabled
Reset on MR0: the TC will be reset if MR0 matches it.
Feature disabled.
Stop on MR0: the TC and PC will be stopped and TCR[0] will be
set to 0 if MR0 matches the TC.
Feature disabled.
Interrupt on MR1: an interrupt is generated when MR1 matches
the value in the TC.
This interrupt is disabled
Reset on MR1: the TC will be reset if MR1 matches it.
Feature disabled.
Stop on MR1: the TC and PC will be stopped and TCR[0] will be
set to 0 if MR1 matches the TC.
Feature disabled.
Interrupt on MR2: an interrupt is generated when MR2 matches
the value in the TC.
This interrupt is disabled
Reset on MR2: the TC will be reset if MR2 matches it.
Feature disabled.
Stop on MR2: the TC and PC will be stopped and TCR[0] will be
set to 0 if MR2 matches the TC.
Feature disabled.
Interrupt on MR3: an interrupt is generated when MR3 matches
the value in the TC.
This interrupt is disabled
Reset on MR3: the TC will be reset if MR3 matches it.
Feature disabled.
Stop on MR3: the TC and PC will be stopped and TCR[0] will be
set to 0 if MR3 matches the TC.
Feature disabled.
Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.
Chapter 24: LPC24XX Timer0/1/2/3
UM10237
© NXP B.V. 2009. All rights reserved.
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Reset
Value
0
0
0
0
0
0
0
0
0
0
0
0
NA