C8051F320DK Silicon Laboratories Inc, C8051F320DK Datasheet - Page 118

• Manufacturer Part Number: C8051F320DK
• Description: DEV KIT FOR C8051F320/F321
• Manufacturer: Silicon Laboratories Inc
• Type: MCUr

Specifications of C8051F320DK

• Contents: Evaluation Board, Power Supply, USB Cables, Adapter and Documentation
• Processor To Be Evaluated: C8051F320/F321
• Interface Type: USB
• Silicon Manufacturer: Silicon Labs
• Core Architecture: 8051
• Silicon Core Number: C8051F320
• Silicon Family Name: C8051F32x
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: Silicon Laboratories C8051F320, C8051F321
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1260

C8051F320/1
Important Note: If the sum of the reset value of OSCICL and OSCICL is greater than 31 or less than 0,
then the device will not be capable of producing the desired frequency.
13.1.2. Internal Oscillator Suspend Mode
The internal oscillator may be placed in Suspend mode by writing ‘1’ to the SUSPEND bit in register
OSCICN. In Suspend mode, the internal oscillator is stopped until a non-idle USB event is detected (Sec-
tion 15) or VBUS matches the polarity selected by the VBPOL bit in register REG0CN (Section 8.2). The
transceiver is able to detect non-idle USB events even when it is placed in Suspend mode. On a non-idle
USB event, a Resume interrupt is generated, on receipt of which the PHYEN bit should be set to '1' to re-
enable the transceiver.
118
Note: The contents of this register are undefined when Clock Recovery is enabled. See Section “15.4. USB Clock
Bit7:
Bit6:
Bit5:
Bits4–2: UNUSED. Read = 000b, Write = don't care.
Bits1–0: IFCN1–0: Internal Oscillator Frequency Control Bits.
Bits7–5: Unused: Read = varies. Write = don’t care.
Bits4–0: OSCCAL: Oscillator Calibration Value
IOSCEN
R/W
R/W
Bit7
Bit7
-
Configuration” on page 146 for details on Clock Recovery.
IOSCEN: Internal Oscillator Enable Bit.
0: Internal Oscillator Disabled.
1: Internal Oscillator Enabled.
IFRDY: Internal Oscillator Frequency Ready Flag.
0: Internal Oscillator is not running at programmed frequency.
1: Internal Oscillator is running at programmed frequency.
SUSPEND: Force Suspend
Writing a ‘1’ to this bit will force the internal oscillator to be stopped. The oscillator will be re-
started on the next non-idle USB event (i.e., RESUME signaling) or VBUS interrupt event
(see Figure 8.1).
00: SYSCLK derived from Internal Oscillator divided by 8.
01: SYSCLK derived from Internal Oscillator divided by 4.
10: SYSCLK derived from Internal Oscillator divided by 2.
11: SYSCLK derived from Internal Oscillator divided by 1.
These bits determine the internal oscillator period as per Equation 13.1.
SFR Definition 13.2. OSCICL: Internal Oscillator Calibration
IFRDY
SFR Definition 13.1. OSCICN: Internal Oscillator Control
R/W
Bit6
Bit6
R
-
SUSPEND
R/W
R/W
Bit5
Bit5
-
R/W
Bit4
Bit4
R
-
Rev. 1.4
R/W
R/W
Bit3
Bit3
-
OSCCAL
R/W
Bit2
R/W
Bit2
-
IFCN1
R/W
Bit1
R/W
Bit1
IFCN0
R/W
Bit0
R/W
Bit0
SFR Address:
SFR Address:
10000000
Reset Value
Reset Value
Variable
0xB2
0xB3