C8051F320DK Silicon Laboratories Inc, C8051F320DK Datasheet - Page 148

• Manufacturer Part Number: C8051F320DK
• Description: DEV KIT FOR C8051F320/F321
• Manufacturer: Silicon Laboratories Inc
• Type: MCUr

Specifications of C8051F320DK

• Contents: Evaluation Board, Power Supply, USB Cables, Adapter and Documentation
• Processor To Be Evaluated: C8051F320/F321
• Interface Type: USB
• Silicon Manufacturer: Silicon Labs
• Core Architecture: 8051
• Silicon Core Number: C8051F320
• Silicon Family Name: C8051F32x
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: Silicon Laboratories C8051F320, C8051F321
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1260

C8051F320/1
15.5.2. FIFO Double Buffering
FIFO slots for Endpoints1-3 can be configured for double-buffered mode. In this mode, the maximum
packet size is halved and the FIFO may contain two packets at a time. This mode is available for
Endpoints1-3. When an endpoint is configured for Split Mode, double buffering may be enabled for the IN
Endpoint and/or the OUT endpoint. When Split Mode is not enabled, double-buffering may be enabled for
the entire endpoint FIFO. See Table 15.3 for a list of maximum packet sizes for each FIFO configuration.
15.5.1. FIFO Access
Each endpoint FIFO is accessed through a corresponding FIFOn register. A read of an endpoint FIFOn
register unloads one byte from the FIFO; a write of an endpoint FIFOn register loads one byte into the end-
point FIFO. When an endpoint FIFO is configured for Split Mode, a read of the endpoint FIFOn register
unloads one byte from the OUT endpoint FIFO; a write of the endpoint FIFOn register loads one byte into
the IN endpoint FIFO.
148
Endpoint
Number
R/W
Bit7
0
1
2
3
USB Register Definition 15.6. FIFOn: USB0 Endpoint FIFO Access
USB Addresses 0x20–0x23 provide access to the 4 pairs of endpoint FIFOs:
Writing to the FIFO address loads data into the IN FIFO for the corresponding endpoint.
Reading from the FIFO address unloads data from the OUT FIFO for the corresponding
endpoint.
IN/OUT Endpoint FIFO
Split Mode
Enabled?
R/W
Bit6
N/A
N
Y
N
Y
N
Y
0
1
2
3
Maximum IN Packet Size (Double
R/W
Bit5
Buffer Disabled/Enabled)
Table 15.3. FIFO Configurations
R/W
Bit4
256/128
FIFODATA
128/64
USB Address
64/32
0x20
0x21
0x22
0x23
Rev. 1.4
R/W
Bit3
256/128
512/256
128/64
R/W
Bit2
64
Maximum OUT Packet Size (Double
Buffer Disabled/Enabled)
R/W
Bit1
256/128
128/64
64/32
R/W
Bit0
0x20 - 0x23
USB Address:
00000000
Reset Value