C8051F320DK Silicon Laboratories Inc, C8051F320DK Datasheet - Page 161

• Manufacturer Part Number: C8051F320DK
• Description: DEV KIT FOR C8051F320/F321
• Manufacturer: Silicon Laboratories Inc
• Type: MCUr

Specifications of C8051F320DK

• Contents: Evaluation Board, Power Supply, USB Cables, Adapter and Documentation
• Processor To Be Evaluated: C8051F320/F321
• Interface Type: USB
• Silicon Manufacturer: Silicon Labs
• Core Architecture: 8051
• Silicon Core Number: C8051F320
• Silicon Family Name: C8051F32x
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: Silicon Laboratories C8051F320, C8051F321
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1260

15.11. Configuring Endpoints1–3
Endpoints1-3 are configured and controlled through their own sets of the following control/status registers:
IN registers EINCSRL and EINCSRH, and OUT registers EOUTCSRL and EOUTCSRH. Only one set of
endpoint control/status registers is mapped into the USB register address space at a time, defined by the
contents of the INDEX register (Figure 15.4).
Endpoints1-3 can be configured as IN, OUT, or both IN/OUT (Split Mode) as described in Section 15.5.1.
The endpoint mode (Split/Normal) is selected via the SPLIT bit in register EINCSRH.
When SPLIT = ‘1’, the corresponding endpoint FIFO is split, and both IN and OUT pipes are available.
When SPLIT = ‘0’, the corresponding endpoint functions as either IN or OUT; the endpoint direction is
selected by the DIRSEL bit in register EINCSRH.
15.12. Controlling Endpoints1–3 IN
Endpoints1-3 IN are managed via USB registers EINCSRL and EINCSRH. All IN endpoints can be used
for Interrupt, Bulk, or Isochronous transfers. Isochronous (ISO) mode is enabled by writing ‘1’ to the ISO bit
in register EINCSRH. Bulk and Interrupt transfers are handled identically by hardware.
An Endpoint1-3 IN interrupt is generated by any of the following conditions:
15.12.1.Endpoints1-3 IN Interrupt or Bulk Mode
When the ISO bit (EINCSRH.6) = ‘0’ the target endpoint operates in Bulk or Interrupt Mode. Once an end-
point has been configured to operate in Bulk/Interrupt IN mode (typically following an Endpoint0
SET_INTERFACE command), firmware should load an IN packet into the endpoint IN FIFO and set the
INPRDY bit (EINCSRL.0). Upon reception of an IN token, hardware will transmit the data, clear the
INPRDY bit, and generate an interrupt.
Writing ‘1’ to INPRDY without writing any data to the endpoint FIFO will cause a zero-length packet to be
transmitted upon reception of the next IN token.
Bit7:
Bits6–0: E0CNT: Endpoint 0 Data Count
Bit7
R
-
1. An IN packet is successfully transferred to the host.
2. Software writes ‘1’ to the FLUSH bit (EINCSRL.3) when the target FIFO is not empty.
3. Hardware generates a STALL condition.
USB Register Definition 15.18. E0CNT: USB0 Endpoint 0 Data Count
Unused. Read = 0b; Write = don’t care.
This 7-bit number indicates the number of received data bytes in the Endpoint 0 FIFO. This
number is only valid while bit OPRDY is a ‘1’.
Bit6
R
Bit5
R
Bit4
R
Rev. 1.4
E0CNT
Bit3
R
Bit2
R
Bit1
R
C8051F320/1
Bit0
R
USB Address:
00000000
Reset Value
0x16
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