C8051F320DK Silicon Laboratories Inc, C8051F320DK Datasheet - Page 195

• Manufacturer Part Number: C8051F320DK
• Description: DEV KIT FOR C8051F320/F321
• Manufacturer: Silicon Laboratories Inc
• Type: MCUr

Specifications of C8051F320DK

• Contents: Evaluation Board, Power Supply, USB Cables, Adapter and Documentation
• Processor To Be Evaluated: C8051F320/F321
• Interface Type: USB
• Silicon Manufacturer: Silicon Labs
• Core Architecture: 8051
• Silicon Core Number: C8051F320
• Silicon Family Name: C8051F32x
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: Silicon Laboratories C8051F320, C8051F321
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1260

18. Enhanced Serial Peripheral Interface (SPI0)
The Enhanced Serial Peripheral Interface (SPI0) provides access to a flexible, full-duplex synchronous
serial bus. SPI0 can operate as a master or slave device in both 3-wire or 4-wire modes, and supports mul-
tiple masters and slaves on a single SPI bus. The slave-select (NSS) signal can be configured as an input
to select SPI0 in slave mode, or to disable Master Mode operation in a multi-master environment, avoiding
contention on the SPI bus when more than one master attempts simultaneous data transfers. NSS can
also be configured as a chip-select output in master mode, or disabled for 3-wire operation. Additional gen-
eral purpose port I/O pins can be used to select multiple slave devices in master mode.
SYSCLK
Clock Divide
SPI0CKR
SFR Bus
SPI0DAT
Logic
Write
Transmit Data Buffer
Receive Data Buffer
Figure 18.1. SPI Block Diagram
7
6
Shift Register
5
SPI CONTROL LOGIC
4
3
Data Path
2
SFR Bus
SPI0CFG
Control
SPI0DAT
1
SPI0DAT
Read
0
Rev. 1.4
Tx Data
Rx Data
Pin Interface
Control
Control
Logic
Pin
SPI0CN
MOSI
MISO
SCK
NSS
O
C
R
S
S
B
A
R
C8051F320/1
SPI IRQ
Port I/O
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