C8051F320DK Silicon Laboratories Inc, C8051F320DK Datasheet - Page 188

• Manufacturer Part Number: C8051F320DK
• Description: DEV KIT FOR C8051F320/F321
• Manufacturer: Silicon Laboratories Inc
• Type: MCUr

Specifications of C8051F320DK

• Contents: Evaluation Board, Power Supply, USB Cables, Adapter and Documentation
• Processor To Be Evaluated: C8051F320/F321
• Interface Type: USB
• Silicon Manufacturer: Silicon Labs
• Core Architecture: 8051
• Silicon Core Number: C8051F320
• Silicon Family Name: C8051F32x
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: Silicon Laboratories C8051F320, C8051F321
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1260

C8051F320/1
17.1. Enhanced Baud Rate Generation
The UART0 baud rate is generated by Timer 1 in 8-bit auto-reload mode. The TX clock is generated by
TL1; the RX clock is generated by a copy of TL1 (shown as RX Timer in Figure 17.2), which is not user-
accessible. Both TX and RX Timer overflows are divided by two to generate the TX and RX baud rates.
The RX Timer runs when Timer 1 is enabled, and uses the same reload value (TH1). However, an
RX Timer reload is forced when a START condition is detected on the RX pin. This allows a receive to
begin any time a START is detected, independent of the TX Timer state.
Timer 1 should be configured for Mode 2, 8-bit auto-reload (see Section “19.1.3. Mode 2: 8-bit Coun-
ter/Timer with Auto-Reload” on page 211). The Timer 1 reload value should be set so that overflows will
occur at two times the desired UART baud rate frequency. Note that Timer 1 may be clocked by one of six
sources: SYSCLK, SYSCLK / 4, SYSCLK / 12, SYSCLK / 48, the external oscillator clock / 8, or an exter-
nal input T1. For any given Timer 1 clock source, the UART0 baud rate is determined by Equation 17.1.
Where T1
value). Timer 1 clock frequency is selected as described in Section “19. Timers” on page 209. A quick ref-
erence for typical baud rates and system clock frequencies is given in Table 17.1. Note that the internal
oscillator may still generate the system clock when the external oscillator is driving Timer 1.
17.2. Operational Modes
UART0 provides standard asynchronous, full duplex communication. The UART mode (8-bit or 9-bit) is
selected by the S0MODE bit (SCON0.7). Typical UART connection options are shown below.
188
CLK
is the frequency of the clock supplied to Timer 1, and T1H is the high byte of Timer 1 (reload
Detected
Start
Figure 17.2. UART0 Baud Rate Logic
RX Timer
Equation 17.1. UART0 Baud Rate
UartBaudRate
Timer 1
TH1
TL1
Overflow
Overflow
Rev. 1.4
=
------------------------------ -

256 T1H
T1
–
CLK
2
2


UART
1
-- -
2
RX Clock
TX Clock