C8051F320DK Silicon Laboratories Inc, C8051F320DK Datasheet - Page 126

• Manufacturer Part Number: C8051F320DK
• Description: DEV KIT FOR C8051F320/F321
• Manufacturer: Silicon Laboratories Inc
• Type: MCUr

Specifications of C8051F320DK

• Contents: Evaluation Board, Power Supply, USB Cables, Adapter and Documentation
• Processor To Be Evaluated: C8051F320/F321
• Interface Type: USB
• Silicon Manufacturer: Silicon Labs
• Core Architecture: 8051
• Silicon Core Number: C8051F320
• Silicon Family Name: C8051F32x
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: Silicon Laboratories C8051F320, C8051F321
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1260

C8051F320/1
14. Port Input/Output
Digital and analog resources are available through 25 I/O pins (C8051F320) or 21 I/O pins (C8051F321).
Port pins are organized as shown in Figure 14.1. Each of the Port pins can be defined as general-purpose
I/O (GPIO) or analog input; Port pins P0.0-P2.3 can be assigned to one of the internal digital resources as
shown in Figure 14.3. The designer has complete control over which functions are assigned, limited only
by the number of physical I/O pins. This resource assignment flexibility is achieved through the use of a
Priority Crossbar Decoder. Note that the state of a Port I/O pin can always be read in the corresponding
Port latch, regardless of the Crossbar settings.
The Crossbar assigns the selected internal digital resources to the I/O pins based on the Priority Decoder
(Figure 14.3 and Figure 14.4). The registers XBR0 and XBR1, defined in Figure 14.1 and Figure 14.2, are
used to select internal digital functions.
All Port I/Os are 5 V tolerant (refer to Figure 14.2 for the Port cell circuit). The Port I/O cells are configured
as either push-pull or open-drain in the Port Output Mode registers (PnMDOUT, where n = 0,1,2,3). Com-
plete Electrical Specifications for Port I/O are given in Table 14.1 on page 138.
126
Highest
Lowest
Priority
Priority
SYSCLK
Outputs
Outputs
SMBus
T0, T1
UART
P0
P1
P2
P3
PCA
CP0
CP1
SPI
Figure 14.1. Port I/O Functional Block Diagram
(P0.0-P0.7)
(P1.0-P1.7)
(P2.0-P2.7)
(P3.0)
2
4
2
2
2
6
2
8
8
8
8
Rev. 1.4
PnSKIP Registers
XBR0, XBR1,
Crossbar
Decoder
Priority
Digital
8
8
8
1
PnMDIN Registers
PnMDOUT,
Cells
Cells
Cells
Cells
Note: P2.4-P2.7 only available
I/O
I/O
I/O
I/O
P0
P1
P2
P3
on the C8051F320
P0.0
P0.7
P1.0
P1.7
P2.0
P2.7
P3.0