C8051F320DK Silicon Laboratories Inc, C8051F320DK Datasheet - Page 166

• Manufacturer Part Number: C8051F320DK
• Description: DEV KIT FOR C8051F320/F321
• Manufacturer: Silicon Laboratories Inc
• Type: MCUr

Specifications of C8051F320DK

• Contents: Evaluation Board, Power Supply, USB Cables, Adapter and Documentation
• Processor To Be Evaluated: C8051F320/F321
• Interface Type: USB
• Silicon Manufacturer: Silicon Labs
• Core Architecture: 8051
• Silicon Core Number: C8051F320
• Silicon Family Name: C8051F32x
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: Silicon Laboratories C8051F320, C8051F321
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1260

C8051F320/1
USB Register Definition 15.21. EOUTCSRL: USB0 OUT Endpoint Control High Byte
166
Bit7:
Bit6:
Bit5:
Bit4:
Bit3:
Bit2:
Bit1:
Bit0:
CLRDT
Bit7
W
CLRDT: Clear Data Toggle
Write: Software should write ‘1’ to this bit to reset the OUT endpoint data toggle to ‘0’.
Read: This bit always reads ‘0’.
STSTL: Sent Stall
Hardware sets this bit to ‘1’ when a STALL handshake signal is transmitted. This flag must
be cleared by software.
SDSTL: Send Stall
Software should write ‘1’ to this bit to generate a STALL handshake. Software should write
‘0’ to this bit to terminate the STALL signal. This bit has no effect in ISO mode.
FLUSH: FIFO Flush
Writing a ‘1’ to this bit flushes the next packet to be read from the OUT endpoint FIFO. The
FIFO pointer is reset and the OPRDY bit is cleared. If the FIFO contains multiple packets,
software must write ‘1’ to FLUSH for each packet. Hardware resets the FLUSH bit to ‘0’
when the FIFO flush is complete.
DATERR: Data Error
In ISO mode, this bit is set by hardware if a received packet has a CRC or bit-stuffing error.
It is cleared when software clears OPRDY. This bit is only valid in ISO mode.
OVRUN: Data Overrun
This bit is set by hardware when an incoming data packet cannot be loaded into the OUT
endpoint FIFO. This bit is only valid in ISO mode, and must be cleared by software.
0: No data overrun.
1: A data packet was lost because of a full FIFO since this flag was last cleared.
FIFOFUL: OUT FIFO Full
This bit indicates the contents of the OUT FIFO. If double buffering is enabled for the end-
point (DBIEN = ‘1’), the FIFO is full when the FIFO contains two packets. If DBIEN = ‘0’, the
FIFO is full when the FIFO contains one packet.
0: OUT endpoint FIFO is not full.
1: OUT endpoint FIFO is full.
OPRDY: OUT Packet Ready
Hardware sets this bit to ‘1’ and generates an interrupt when a data packet is available. Soft-
ware should clear this bit after each data packet is unloaded from the OUT endpoint FIFO.
STSTL
R/W
Bit6
SDSTL
R/W
Bit5
FLUSH
Bit4
W
DATERR
Rev. 1.4
Bit3
R
OVRUN
R/W
Bit2
FIFOFUL
Bit1
R
OPRDY
R/W
Bit0
USB Address:
00000000
Reset Value
0x14