C8051F320DK Silicon Laboratories Inc, C8051F320DK Datasheet - Page 223

• Manufacturer Part Number: C8051F320DK
• Description: DEV KIT FOR C8051F320/F321
• Manufacturer: Silicon Laboratories Inc
• Type: MCUr

Specifications of C8051F320DK

• Contents: Evaluation Board, Power Supply, USB Cables, Adapter and Documentation
• Processor To Be Evaluated: C8051F320/F321
• Interface Type: USB
• Silicon Manufacturer: Silicon Labs
• Core Architecture: 8051
• Silicon Core Number: C8051F320
• Silicon Family Name: C8051F32x
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: Silicon Laboratories C8051F320, C8051F321
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1260

19.3.2. 8-bit Timers with Auto-Reload
When T3SPLIT is set, Timer 3 operates as two 8-bit timers (TMR3H and TMR3L). Both 8-bit timers oper-
ate in auto-reload mode as shown in Figure 19.5. TMR3RLL holds the reload value for TMR3L; TMR3RLH
holds the reload value for TMR3H. The TR3 bit in TMR3CN handles the run control for TMR3H. TMR3L is
always running when configured for 8-bit Mode.
Each 8-bit timer may be configured to use SYSCLK, SYSCLK divided by 12, or the external oscillator clock
source divided by 8. The Timer 3 Clock Select bits (T3MH and T3ML in CKCON) select either SYSCLK or
the clock defined by the Timer 3 External Clock Select bit (T3XCLK in TMR3CN), as follows:
The TF3H bit is set when TMR3H overflows from 0xFF to 0x00; the TF3L bit is set when TMR3L overflows
from 0xFF to 0x00. When Timer 3 interrupts are enabled, an interrupt is generated each time TMR3H over-
flows. If Timer 3 interrupts are enabled and TF3LEN (TMR3CN.5) is set, an interrupt is generated each
time either TMR3L or TMR3H overflows. When TF3LEN is enabled, software must check the TF3H and
TF3L flags to determine the source of the Timer 3 interrupt. The TF3H and TF3L interrupt flags are not
cleared by hardware and must be manually cleared by software.
External Clock / 8
T3MH
0
0
1
SYSCLK / 12
T3XCLK
T3XCLK
0
1
X
0
1
Figure 19.9. Timer 3 8-Bit Mode Block Diagram
TMR3H Clock Source
SYSCLK
External Clock / 8
SYSCLK / 12
SYSCLK
0
1
1
0
T
M
H
3
M
T
3
L
CKCON
M
T
2
H
M
T
2
L
TR3
M
T
1
M
T
0
C
S
A
1
S
C
A
0
Rev. 1.4
TCLK
TCLK
TMR3RLH
TMR3RLL
TMR3H
TMR3L
T3ML
0
0
1
Reload
Reload
T3XCLK
X
0
1
To ADC
T3SPLIT
T3XCLK
TF3LEN
T3SOF
C8051F320/1
TF3H
TF3L
TR3
TMR3L Clock Source
External Clock / 8
SYSCLK / 12
SYSCLK
Interrupt
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