US38024-BAG1 Renesas Electronics America, US38024-BAG1 Datasheet - Page 163

• Manufacturer Part Number: US38024-BAG1
• Description: DEV EVALUATION KIT H8/38024
• Manufacturer: Renesas Electronics America
• Series: H8®r
• Type: MCUr

Specifications of US38024-BAG1

• Contents: 2G (Second-generation) Evaluation Board, HEW debugger support, Cable and CD-ROM
• For Use With/related Products: H8/38024
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

2. Time for direct transition from active (medium-speed) mode to active (high-speed) mode
A direct transition from active (medium-speed) mode to active (high-speed) mode is performed by
executing a SLEEP instruction in active (medium-speed) mode while bits SSBY and LSON are
both cleared to 0 in SYSCR1, and bit MSON is cleared to 0 and bit DTON is set to 1 in SYSCR2.
The time from execution of the SLEEP instruction to the end of interrupt exception handling (the
direct transition time) is given by equation (2) below.
Direct transition time = { (Number of SLEEP instruction execution states) + (number of internal
Example: Direct transition time = (2 + 1) × 16tosc + 14 × 2tosc = 76tosc (when φ/8 is selected as
[Legend]
tosc: OSC clock cycle time
tcyc: System clock (φ) cycle time
3. Time for direct transition from subactive mode to active (high-speed) mode
A direct transition from subactive mode to active (high-speed) mode is performed by executing a
SLEEP instruction in subactive mode while bit SSBY is set to 1 and bit LSON is cleared to 0 in
SYSCR1, bit MSON is cleared to 0 and bit DTON is set to 1 in SYSCR2, and bit TMA3 is set to 1
in TMA. The time from execution of the SLEEP instruction to the end of interrupt exception
handling (the direct transition time) is given by equation (3) below.
Direct transition time = { (Number of SLEEP instruction execution states) + (number of internal
Example: Direct transition time = (2 + 1) × 8tw + (8192 + 14) × 2tosc = 24tw + 16412tosc (when
[Legend]
tosc:
tw:
tcyc:
tsubcyc: Subclock (φ
OSC clock cycle time
Watch clock cycle time
System clock (φ) cycle time
the CPU operating clock)
φw/8 is selected as the CPU operating clock, and wait time = 8192 states)
SUB
processing states) } × (tsubcyc before transition) + { (wait time set in
STS2 to STS0) + (number of interrupt exception handling execution
states) } × (tcyc after transition)
processing states) } × (tcyc before transition) + (number of interrupt
exception handling execution states) × (tcyc after transition)
) cycle time
Rev. 8.00 Mar. 09, 2010 Page 141 of 658
Section 5 Power-Down Modes
.................................. (2)
REJ09B0042-0800
........................ (3)