US38024-BAG1 Renesas Electronics America, US38024-BAG1 Datasheet - Page 79

• Manufacturer Part Number: US38024-BAG1
• Description: DEV EVALUATION KIT H8/38024
• Manufacturer: Renesas Electronics America
• Series: H8®r
• Type: MCUr

Specifications of US38024-BAG1

• Contents: 2G (Second-generation) Evaluation Board, HEW debugger support, Cable and CD-ROM
• For Use With/related Products: H8/38024
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Three-state access to on-chip peripheral modules
2.7
2.7.1
There are four CPU states: the reset state, program execution state, program halt state, and
exception-handling state. The program execution state includes active (high-speed or medium-
speed) mode and subactive mode. In the program halt state there are a sleep (high-speed or
medium-speed) mode, standby mode, watch mode, and sub-sleep mode. These states are shown in
figure 2.14. Figure 2.15 shows the state transitions.
φ or φ
Internal
address bus
Internal
read signal
Internal
data bus
(read access)
Internal
write signal
Internal
data bus
(write access)
SUB
Overview
CPU States
Figure 2.13 On-Chip Peripheral Module Access Cycle (3-State Access)
T
1
state
Address
Bus cycle
T
2
state
Read data
Write data
Rev. 8.00 Mar. 09, 2010 Page 57 of 658
T
3
state
REJ09B0042-0800
Section 2 CPU