US38024-BAG1 Renesas Electronics America, US38024-BAG1 Datasheet - Page 629

• Manufacturer Part Number: US38024-BAG1
• Description: DEV EVALUATION KIT H8/38024
• Manufacturer: Renesas Electronics America
• Series: H8®r
• Type: MCUr

Specifications of US38024-BAG1

• Contents: 2G (Second-generation) Evaluation Board, HEW debugger support, Cable and CD-ROM
• For Use With/related Products: H8/38024
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

IRR2—Interrupt Request Register 2
Bit
Initial value
Read/Write
Note: * Bits 7, 6, and 4 to 0 can only be written with 0, for flag clearing.
Direct Transition Interrupt Request Flag
0 Clearing condition:
1 Setting condition:
When IRRDT = 1, it is cleared by writing 0
When a SLEEP instruction is executed while DTON is set to 1, and a direct transition is made
IRRDT
R/(W) *
7
0
A/D Converter Interrupt Request Flag
0 Clearing condition:
1 Setting condition:
When IRRAD = 1, it is cleared by writing 0
When the A/D converter completes conversion and ADSF is reset
Timer G Interrupt Request Flag
IRRAD
R/(W) *
0 Clearing condition:
1 Setting conditions:
When IRRTG = 1, it is cleared by writing 0
When the TMIG pin is designated for TMIG input and the designated signal edge is
input, and when TCG overflows while OVIE is set to 1 in TMG
6
0
Timer FH Interrupt Request Flag
0 Clearing condition:
1 Setting conditions:
When IRRTFH = 1, it is cleared by writing 0
When counter FH and output compare register FH match in 8-bit timer mode,
or when 16-bit counters FL and FH and output compare registers FL and
FH match in 16-bit timer mode
⎯
⎯
W
5
Timer FL Interrupt Request Flag
0 Clearing condition:
1 Setting condition:
IRRTG
R/(W) *
When IRRTFL = 1, it is cleared by writing 0
When counter FL and output compare register FL match in 8-bit
timer mode
4
0
Timer C Interrupt Request Flag
0 Clearing condition:
1 Setting condition:
When IRRTC = 1, it is cleared by writing 0
When the timer C counter value overflows (from H'FF to
H'00) or underflows (from H'00 to H'FF)
Asynchronous Event Counter Interrupt Request Flag
IRRTFH
0 Clearing condition:
1 Setting condition:
R/(W) *
Rev. 8.00 Mar. 09, 2010 Page 607 of 658
When the asynchronous event counter value
overflows
When IRREC = 1, it is cleared by writing 0
3
0
H'F7
Appendix B Internal I/O Registers
IRRTFL
R/(W) *
2
0
R/(W) *
IRRTC
1
0
REJ09B0042-0800
System Control
IRREC
R/(W) *
0
0