US38024-BAG1 Renesas Electronics America, US38024-BAG1 Datasheet - Page 389

• Manufacturer Part Number: US38024-BAG1
• Description: DEV EVALUATION KIT H8/38024
• Manufacturer: Renesas Electronics America
• Series: H8®r
• Type: MCUr

Specifications of US38024-BAG1

• Contents: 2G (Second-generation) Evaluation Board, HEW debugger support, Cable and CD-ROM
• For Use With/related Products: H8/38024
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

SCI3 operates as follows when transmitting data.
SCI3 monitors bit TDRE in SSR, and when it is cleared to 0, recognizes that data has been written
to TDR and transfers data from TDR to TSR. It then sets bit TDRE to 1 and starts transmitting. If
bit TIE in SCR3 is set to 1 at this time, a TXI request is made.
Serial data is transmitted from the TXD
When the stop bit is sent, SCI3 checks bit TDRE. If bit TDRE is cleared to 0, SCI3 transfers data
from TDR to TSR, and when the stop bit has been sent, starts transmission of the next frame. If
bit TDRE is set to 1, bit TEND in SSR bit is set to 1the mark state, in which 1s are transmitted, is
established after the stop bit has been sent. If bit TEIE in SCR3 is set to 1 at this time, a TEI
request is made.
Figure 10.7 shows an example of the operation when transmitting in asynchronous mode.
Serial
data
TDRE
TEND
LSI
operation
User
processing
Figure 10.7 Example of Operation when Transmitting in Asynchronous Mode
TXI request
1
Start
bit
0
D0
D1
TDRE
cleared to 0
Data written
to TDR
Transmit
1 frame
data
(8-bit data, parity, 1 stop bit)
D7
32
Parity
pin using the relevant data transfer format in table 10.11.
0/1
bit
TXI request
Stop
bit
1
Start
bit
0
Section 10 Serial Communication Interface
Rev. 8.00 Mar. 09, 2010 Page 367 of 658
D0
1 frame
D1
Transmit
data
D7
Parity
0/1
bit
REJ09B0042-0800
TEI request
Stop
bit
1
Mark
state
1