US38024-BAG1 Renesas Electronics America, US38024-BAG1 Datasheet - Page 398

• Manufacturer Part Number: US38024-BAG1
• Description: DEV EVALUATION KIT H8/38024
• Manufacturer: Renesas Electronics America
• Series: H8®r
• Type: MCUr

Specifications of US38024-BAG1

• Contents: 2G (Second-generation) Evaluation Board, HEW debugger support, Cable and CD-ROM
• For Use With/related Products: H8/38024
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Section 10 Serial Communication Interface
SCI3 operates as follows when receiving data.
SCI3 performs internal synchronization and begins reception in synchronization with the serial
clock input or output.
The received data is placed in RSR in LSB-to-MSB order.
After the data has been received, SCI3 checks that bit RDRF is set to 0, indicating that the receive
data can be transferred from RSR to RDR.
If this check shows that there is no overrun error, bit RDRF is set to 1, and the receive data is
stored in RDR. If bit RIE is set to 1 in SCR3, an RXI interrupt is requested. If the check
identifies an overrun error, bit OER is set to 1.
Bit RDRF remains set to 1. If bit RIE is set to 1 in SCR3, an ERI interrupt is requested.
See table 10.12 for the conditions for detecting a receive error, and receive data processing.
Note: No further receive operations are possible while a receive error flag is set. Bits OER,
Figure 10.14 shows an example of the operation when receiving in synchronous mode.
Rev. 8.00 Mar. 09, 2010 Page 376 of 658
REJ09B0042-0800
RDRF
OER
LSI
operation
User
processing
Serial
clock
Serial
data
FER, PER, and RDRF must therefore be cleared to 0 before resuming reception.
Figure 10.14 Example of Operation when Receiving in Synchronous Mode
RXI request
Bit 7
Bit 0
RDRE cleared
to 0
RDR data read
1 frame
Bit 7
RXI request
Bit 0
Bit 1
1 frame
RDR data has
not been read
(RDRF = 1)
Bit 6
ERI request in
response to
overrun error
Overrun error
processing
Bit 7