US38024-BAG1 Renesas Electronics America, US38024-BAG1 Datasheet - Page 77

• Manufacturer Part Number: US38024-BAG1
• Description: DEV EVALUATION KIT H8/38024
• Manufacturer: Renesas Electronics America
• Series: H8®r
• Type: MCUr

Specifications of US38024-BAG1

• Contents: 2G (Second-generation) Evaluation Board, HEW debugger support, Cable and CD-ROM
• For Use With/related Products: H8/38024
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

2.6
CPU operation is synchronized by a system clock (φ) or a subclock (φ
clock signals see section 4, Clock Pulse Generators. The period from a rising edge of φ or φ
the next rising edge is called one state. A bus cycle consists of two states or three states. The
cycle differs depending on whether access is to on-chip memory or to on-chip peripheral modules.
2.6.1
Access to on-chip memory takes place in two states. The data bus width is 16 bits, allowing
access in byte or word size. Figure 2.11 shows the on-chip memory access cycle.
φ or φ
Internal address bus
Internal read signal
Internal data bus
(read access)
Internal write signal
Internal data bus
(write access)
Access to On-Chip Memory (RAM, ROM)
Basic Operational Timing
SUB
Figure 2.11 On-Chip Memory Access Cycle
T
1
state
Bus cycle
Address
Rev. 8.00 Mar. 09, 2010 Page 55 of 658
Write data
Read data
T
2
state
SUB
). For details on these
REJ09B0042-0800
Section 2 CPU
SUB
to