US38024-BAG1 Renesas Electronics America, US38024-BAG1 Datasheet - Page 329

• Manufacturer Part Number: US38024-BAG1
• Description: DEV EVALUATION KIT H8/38024
• Manufacturer: Renesas Electronics America
• Series: H8®r
• Type: MCUr

Specifications of US38024-BAG1

• Contents: 2G (Second-generation) Evaluation Board, HEW debugger support, Cable and CD-ROM
• For Use With/related Products: H8/38024
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Bit 2
WDON
0
1
Counting starts when this bit is set to 1, and stops when this bit is cleared to 0.
Bit 1—Bit 0 Write Inhibit (B0WI)
Bit 1 controls the writing of data to bit 0 in TCSRW.
Bit 1
B0WI
0
1
This bit is always read as 1. Data written to this bit is not stored.
Bit 0—Watchdog Timer Reset (WRST)
Bit 0 indicates that TCW has overflowed, generating an internal reset signal. The internal reset
signal generated by the overflow resets the entire chip. WRST is cleared to 0 by a reset from the
RES pin, or when software writes 0.
Bit 0
WRST
0
1
Description
Watchdog timer operation is disabled
Clearing conditions:
Reset, or when TCSRWE is set to 1 and 0 is written to B2WI and WDON. Note that
a reset clears WDON to 0 on the H8/38024, H8/38024S, and H8/38024R Group, but
sets WDON to 1 on the H8/38124 Group.
Note: * Initial value is 0 on H8/38024, H8/38024S, and H8/38024R Group; initial
Watchdog timer operation is enabled
Setting condition:
When TCSRWE is set to 1 and 0 is written to B2WI and 1 is written to WDON
Description
Bit 0 is write-enabled
Bit 0 is write-protected
Description
Clearing conditions:
Reset by RES pin
When TCSRWE = 1, and 0 is written in both BOWI and WRST
Setting condition:
When TCW overflows and an internal reset signal is generated
value is 1 on H8/38124 Group.
Rev. 8.00 Mar. 09, 2010 Page 307 of 658
REJ09B0042-0800
Section 9 Timers
(initial value) *
(initial value)