US38024-BAG1 Renesas Electronics America, US38024-BAG1 Datasheet - Page 78

• Manufacturer Part Number: US38024-BAG1
• Description: DEV EVALUATION KIT H8/38024
• Manufacturer: Renesas Electronics America
• Series: H8®r
• Type: MCUr

Specifications of US38024-BAG1

• Contents: 2G (Second-generation) Evaluation Board, HEW debugger support, Cable and CD-ROM
• For Use With/related Products: H8/38024
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Section 2 CPU
2.6.2
On-chip peripheral modules are accessed in two states or three states. The data bus width is 8 bits,
so access is by byte size only. This means that for accessing word data, two instructions must be
used. Figures 2.12 and 2.13 show the on-chip peripheral module access cycle.
Two-state access to on-chip peripheral modules
Rev. 8.00 Mar. 09, 2010 Page 56 of 658
REJ09B0042-0800
φ or φ
Internal address bus
Internal read signal
Internal data bus
(read access)
Internal write signal
Internal data bus
(write access)
Access to On-Chip Peripheral Modules
Figure 2.12 On-Chip Peripheral Module Access Cycle (2-State Access)
SUB
T
1
state
Bus cycle
Address
Write data
Read data
T
2
state