US38024-BAG1 Renesas Electronics America, US38024-BAG1 Datasheet - Page 186

• Manufacturer Part Number: US38024-BAG1
• Description: DEV EVALUATION KIT H8/38024
• Manufacturer: Renesas Electronics America
• Series: H8®r
• Type: MCUr

Specifications of US38024-BAG1

• Contents: 2G (Second-generation) Evaluation Board, HEW debugger support, Cable and CD-ROM
• For Use With/related Products: H8/38024
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Section 6 ROM
6.6.3
EBR specifies the flash memory erase area block. EBR is initialized to H'00 when the SWE bit in
FLMCR1 is 0. Do not set more than one bit at a time, as this will cause all the bits in EBR to be
automatically cleared to 0. When each bit is set to 1 in EBR, the corresponding block can be
erased. Other blocks change to the erase-protection state. See table 6.6 for the method of dividing
blocks of the flash memory. When the whole bits are to be erased, erase them in turn in unit of a
block.
Table 6.6
EBR
0
1
2
3
4
6.6.4
FLPWCR enables or disables a transition to the flash memory power-down mode when the LSI
switches to subactive mode. The power supply circuit can be read in the subactive mode, although
it is partly halted in the power-down mode.
Rev. 8.00 Mar. 09, 2010 Page 164 of 658
REJ09B0042-0800
Bit
Initial value
Read/Write
Bit
Initial value
Read/Write
Flash Memory Power Control Register (FLPWCR)
Erase Block Register (EBR)
Division of Blocks to Be Erased
Bit Name
EB0
EB1
EB2
EB3
EB4
PDWND
R/W
—
—
7
0
7
0
—
—
—
—
6
0
6
0
Block (Size)
EB0 (1 Kbyte)
EB1 (1 Kbyte)
EB2 (1 Kbyte)
EB3 (1 Kbyte)
EB4 (12 Kbytes)
EB4 (28 Kbytes)
—
—
—
—
5
0
5
0
R/W
EB4
—
—
4
0
4
0
Address
H'0000 to H'03FF
H'0400 to H'07FF
H'0800 to H'0BFF
H'0C00 to H'0FFF
H'1000 to H'3FFF (HD64F38122)
H'1000 to H'7FFF (HD64F38124,
HD64F38024, HD64F38024R)
R/W
EB3
—
—
3
0
3
0
R/W
EB2
—
—
2
0
2
0
R/W
EB1
—
—
1
0
1
0
R/W
EB0
—
—
0
0
0
0